TI380C27 Datasheet, PDF (50/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
SCS, SRSX,
SRS0 – SRS2,
SBHE
Only SCS needs to be inactive.
All others are don’t care.
SIACK
SWR
272a
272a
273a
273a
SRD
SDDIR
High
SDBEN
272a
282R
283R
273a
279
276
275
SRDY
Hi-Z
282a
255
Hi-Z
(see Note A)
259
260
261
261a
SADH0 – SADH7,
SADL0 – SADL7,
Hi-Z
SPH, SPL
(see Note B)
Output Data Valid
Hi-Z
NOTES: A. SRDY is an active-low bus ready signal. It must be asserted before data output.
B. In 8-bit 80x8x mode DIO writes, the value placed on SADH0 – SADH7 is a don’t care.
Figure 24. 80x8x Interrupt-Acknowledge-Cycle Timing: Second SIACK Pulse
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