TI380C27 Datasheet, PDF (11/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
PIN
NAME
NO.
I/O ^†
Pin Functions (Continued)
DESCRIPTION
Intel Mode
SRAS is used for system memory-address strobe (see Note 7). SRAS is used to latch
the SCS and SRSX – SRS2 register input signals. In a minimum-chip system, SRAS is
tied to the SALE output of the system bus. The latching capability can be defeated since
the internal latch for these inputs remains transparent as long as SRAS remains high.
This permits SRAS to be pulled high and the signals at SCS, SRSX – SRS2, and SBHE
to be applied independently of the SALE strobe from the system bus. During DMA, SRAS
remains an input.
SRAS/SAS
SRD/SUDS
60
I/O
H
= Transparent mode
L
= Holds latched values of SCS, SRSX – SRS2, and SBHE
Falling edge = Latches SCS, SRSX – SRS2, and SBHE
Motorola
Mode
SAS is used for sytem-memory address strobe (see Note 7). SAS is an active-low
address strobe that is an input during DIO (although ignored as an address strobe) and
an output during DMA.
H = Address is not valid.
L = Address is valid and a transfer operation is in progress.
SRD is used for system read strobe (see Note 7). SRD is the active-low strobe indicating
that a read cycle is performed on the system bus. SRD is an input during DIO and an
output during DMA.
Intel Mode
H = Read cycle is not occurring.
83
I/O
L = If DMA, host provides data to system bus.
If DIO, SIF provides data to system bus.
Motorola
Mode
SUDS is used for upper-data strobe (see Note 7). SUDS is the active-low upper-data
strobe. SUDS is an input during DIO and an output during DMA.
H = Not valid data on SADH0 – SADH7 lines
L = Valid data on SADH0 – SADH7 lines
Intel Mode
SRDY is used for system bus ready (see Note 7). SRDY indicates to the bus master that
a data transfer is complete. SRDY is asynchronous but during DMA and pseudo-DMA
cycles, it is internally synchronized to SBCLK. During DMA cycles, SRDY must be
asserted before the falling edge of SBCLK in state T2 in order to prevent a wait state.
SRDY is an output when the TI380C27 is selected for DIO; otherwise, it is an input.
SRDY/SDTACK ⁸²
H = System bus is not ready.
L = Data transfer is complete; system bus is ready.
I/O
SDTACK is used for system data-transfer acknowledge (see Note 7). The purpose of
SDTACK is to indicate to the bus master that a data transfer is complete. SDTACK is
internally synchronized to SBCLK. During DMA cycles, SDTACK must be asserted
Motorola before the falling edge of SBCLK in state T2 in order to prevent a wait state. SDTACK
Mode is an output when the TI380C27 is selected for DIO; otherwise, it is an input.
H = System bus is not ready.
L = Data transfer is complete; system bus is ready.
System reset. SRESET is activated to place the TI380C27 into a known initial state. Hardware reset
puts most of the TI380C27 outputs into the high-impedance state and place all blocks into the reset
state. The Intel mode DMA bus-width selection (S8) is latched on the rising edge of SRESET.
SRESET
44
I
H
= No system reset
L
= System reset
Rising edge = Latch bus width for DMA operations (for Intel-mode applications)
† _{I = input, O = output}
NOTE 7: Pin should be tied to VCC with a 4.7-kΩ pullup resistor.
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