TI380C27 Datasheet, PDF (59/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
68xxx DIO read-cycle timing
25-MHz OPERATION
33-MHz OPERATION
NO.
UNIT
MIN
MAX
MIN
MAX
255 Delay time, SDTACK low to either SCS, SUDS, or SLDS high
15
15
ns
259†
Hold time, SAD in the high-impedance state after SUDS or SLDS
low (see Note 24)
0
0
ns
260
Setup time, SADH0 – SADH7, SADL0 – SADL7, SPH, and SPL
valid before SDTACK low
0
0
ns
Delay time, SCS, SUDS, or SLDS high to SADH0 – SADH7,
261† SADL0 – SADL7, SPH, and SPL in the high-impedance state
35
(see Note 24)
35
ns
Hold time, output data valid after SUDS or SLDS no longer low
261a _{(see Note 24)}
0
0
ns
267
Setup time, register address before SUDS or SLDS no longer
high (see Note 24)
15
15
ns
268
Hold time, register address valid after SUDS or SLDS no longer
low (see Note 25)
0
0
ns
272
Setup time, SRNW before SUDS or SLDS no longer high
(see Note 24)
12
12
ns
273 Hold time, SRNW after SUDS or SLDS high
0
0
ns
273a Hold time, SIACK high after SUDS or SLDS high
tc(SCK)
tc(SCK)
ns
275
Delay time, SCS, SUDS, or SLDS high to SDTACK high
(see Note 24)
0
25
0
25
ns
276‡
Delay time, SDTACK low in the first DIO access to the SIF
register to SDTACK low in the immediately following access to
the SIF
4000
4000
ns
279†
Delay time, SUDS or SLDS high to SDTACK in the
high-impedance state
0
tc(SCK)
0
tc(SCK) ns
282a
282R
Delay time, SDBEN low to SDTACK low
Delay time, SUDS or SLDS low to SDBEN low (see TMS380
Second Generation Token-Ring User’s Guide, SPWU005,
subsection 3.4.1.1.1) provided the previous cycle completed
0
tc(SCK) / 2 + 4
0
tc(SCK) + 3
0
tc(SCK) / 2 + 4 ns
0
tc(SCK) + 3 ns
283R Delay time, SUDS or SLDS high to SDBEN high (see Note 24)
0
tc(SCK) / 2 + 4
0
tc(SCK) / 2 + 4 ns
286
Pulse duration, SUDS or SLDS high between DIO accesses
(see Note 24)
tc(SCK)
tc(SCK)
ns
† _{This specification is provided as an aid to board design. It is not assured during manufacturing testing.}
‡ _{This specification has been characterized to meet stated value. It is not assured during manufacturing testing.}
NOTES: 24. The inactive chip select is SIACK in DIO read and DIO write cycles, and SCS is the inactive chip select in interrupt-acknowledge
cycles.
25. In 80x8x mode, SRAS can be used to strobe the values of SBHE, SRSX, SRS0 – SRS2, and SCS. When used to do so, SRAS must
meet parameter 266a, and SBHE, SRS0 – SRS2, and SCS must meet parameter 264. If SRAS is strapped high, parameters 266a
and 264 are irrelevant and parameter 268 must be met.
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