TI380C27 Datasheet, PDF (19/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
protocol handler (PH) (continued)
Integrity of the transmitted and received data is assured by cyclic redundancy checks (CRC), detection of
network data violations, and parity on internal data paths. All data paths and registers are optionally parity
protected to assure functional integrity.
adapter support function (ASF)
The ASF performs support functions not contained in the other blocks. The features are:
• The TI380C27 base timer
• Identification, management, and service of internal and external interrupts
• Test-pin mode control, including the unit-in-place mode for board testing
• Checks for illegal states, such as illegal opcodes and parity
clock generator (CG)
The CG performs the generation of all the clocks required by the other functional blocks, including the local
memory-bus clocks (MBCLK1, MBCLK2). The CG also generates the reference timer used to sample all input
clocks (SBCLK, OSCIN, RCLK, and PXTALIN). If no transition is detected within the period of the reference timer
on any input clock signal, the CG places the TI380C27 into slow-clock mode. The frequency of the reference
timer is in the range of 10 kHz – 100 kHz.
user-accessible hardware registers and TI380C27-internal pointers
The following tables show how to access internal data via pointers and how to address the registers in the host
interface. The SIFACL register, which directly controls device operation, is described in detail. The
adapter-internal pointers table on the following page is defined only after TI380C27 initialization and until the
OPEN command is issued. These pointers are defined by the TI380C27 software (microcode), and this table
describes the release 1.xx and 2.x software.
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