TI380C27 Datasheet, PDF (62/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
SCS SRSX,
SRS0, SRS1
267
SIACK
272
SRNW
SUDS,
SLDS
(see Note A)
272a
Valid
280
268
273a
273
286
273a
SDDIR
High
282W
283W
SDBEN
(see Note B)
276
279
275
SDTACK
(see Note C)
Hi-Z
282b
255
262
Hi-Z
263
SADH0 – SADH7,
SADL0 – SADL7,
SPH, SPL
Hi-Z
Data
See Note C
Hi-Z
NOTES: A. For 68xxx mode, skew between SLDS and SUDS must not exceed 10 ns. Provided this limitation is observed, all events
referenced to a data-strobe edge use the later occurring edge. Events defined by two data strobes edges, such as parameter
286, are measured between latest and earlier edges.
B. When the TI380C27 begins to drive SDBEN inactive, it has already latched the write data internally. Parameter 263 must be
met to the input of the data buffers.
C. SDTACK is an active-low bus ready signal. It must be asserted before data output.
Figure 31. 68xxx DIO Write-Cycle Timing
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