TI380C27 Datasheet, PDF (32/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
memory-bus timing: local-memory clocks, MAL, MROMEN, MBIAEN, NMI, MRESET, and ADDRESS
t_M is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum for a 4-MHz local bus or
20.83 ns minimum for a 6-MHz local bus).
NO.
MIN
MAX UNIT
1 Period of MBCLK1 and MBCLK2
4tM
ns
2 Pulse duration, clock high
2tM – 9
ns
3 Pulse duration, clock low
2tM – 9
ns
4 Hold time, MBCLK2 low after MBCLK1 high
tM – 9
ns
5 Hold time, MBCLK1 high after MBCLK2 high
tM – 9
ns
6 Hold time, MBCLK2 high after MBCLK1 low
tM – 9
ns
7 Hold time, MBCLK1 low after MBCLK2 low
tM – 9
ns
8 Setup time, address/enable on MAX0, MAX2, and MROMEN before MBCLK1 no longer high
tM – 9
ns
9 Setup time, row address on MADL0 – MADL7, MAXPH, and MAXPL before MBCLK1 no longer high
tM – 14
ns
10 Setup time, address on MADH0 – MADH7 before MBCLK1 no longer high
tM – 14
ns
11 Setup time, MAL high before MBCLK1 no longer high
13
ns
12 Setup time, address on MAX0, MAX2, and MROMEN before MBCLK1 no longer low
0.5tM – 9
ns
13
Setup time, column address on MADL0 – MADL7, MAXPH, and MAXPL before MBCLK1 no
longer low
0.5tM – 9
ns
14 Setup time, status on MADH0 – MADH7 before MBCLK1 no longer low
120 Setup time, NMI valid before MBCLK1 low
0.5tM – 9
ns
30
ns
121 Hold time, NMI valid after MBCLK1 low
0
ns
126 Delay time, MBCLK1 no longer low to MRESET valid
0
20 ns
129 Hold time, column address/status after MBCLK1 no longer low
tM – 7
ns
Reference
4 Periods
8 Periods
12 Periods
16 Periods
20 Periods
OSCIN
(when CLKDIV = 1)
OSCIN
(when CLKDIV = 0)
OSCOUT
MBCLK1
See Note A
MBCLK2
See Note A
NOTE A: MBCLK1 and MBCLK2 have no timing relationship to OSCOUT. MBCLK1 and MBCLK2 can start on any OSCIN rising edge,
depending on when the memory cycle starts execution.
Figure 5. Clock Waveforms After Clock Stabilization
32
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