TI380C27 Datasheet, PDF (41/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
token ring: transmitter timing
NO.
MIN MAX UNIT
159 tsk(DR)
Delay from DRVR rising edge (1.8 V ) to DRVR falling edge (1 V ) or DRVR falling edge
(1 V ) to DRVR rising edge (1.8 V )
±2 ns
160 td(DR)H†
Delay from RCLK (or PXTALIN) falling edge (1 V ) to DRVR rising edge (1.8 V )
See Note 18 ns
161 td(DR)L†
Delay from RCLK (or PXTALIN) falling edge (1 V ) to DRVR falling edge (1 V )
See Note 18 ns
162 td(DRN)H†
Delay from RCLK (or PXTALIN) falling edge (1 V ) to DRVR falling edge (1 V )
See Note 18 ns
163 t(DRN)L†
Delay from RCLK (or PXTALIN) falling edge (1 V ) to DRVR rising edge (1.8 V )
164
DRVR / DRVR
asymmetry
) ) t_d(DR)L
t_d(DRN)H
2
– ^td(DR)H
t_d(DRN)L
2
See Note 18 ns
±1.5 ns
† _{When in active-monitor mode, the clock source is PXTALIN; otherwise, the clock-source is either RCLK or PXTALIN.}
NOTE 18: This parameter is not tested to a minimum or a maximum but is measured and used as a component required for parameter 164.
RCLK or PXTALIN
2.6 V
1.5 V
0.6 V
DRVR
DRVR
160
159
162
161
159
163
2.4 V
1.5 V
0.6 V
2.4 V
1.5 V
0.6 V
Figure 13. Skew and Asymmetry From RCLK or PXTALIN to DRVR and DRVR
ethernet timing of clock signals
NO.
300 CLKPHS Pulse duration, TXC
301 CLKPER Cycle time, TXC
MIN MAX UNIT
45
ns
95 1000 ns
TXC
300
301
300
Figure 14. Ethernet Timing of TXC
1.5 V
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