TI380C27 Datasheet, PDF (63/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
68xxx interrupt-acknowledge-cycle timing
25-MHz OPERATION
33-MHz OPERATION
NO.
UNIT
MIN
MAX
MIN
MAX
255 Delay time, SDTACK low to either SCS or SUDS, or SIACK high
15
15
ns
259†
Hold time, SAD in the high-impedance state after SIACK no longer
high (see Note 24)
0
0
ns
260 Setup time, output data valid before SDTACK no longer high
0
0
ns
261†
Delay time, SIACK high to SAD in the high-impedance state
(see Note 24)
35
35
ns
261a
Hold time, output data valid after SCS or SIACK no longer low
(see Note 24)
0
0
ns
267§
Setup time, register address before SIACK no longer high
(see Note 24)
15
15
ns
Setup time, inactive high SIACK to active data strobe no longer
272a _high
tc(SCK)
tc(SCK)
ns
273a Hold time, inactive SRNW high after active data strobe high
tc(SCK)
tc(SCK)
ns
275 Delay time, SCS or SRNW high to SDTACK high (see Note 24)
0
25
0
25
ns
276‡
279†
282a
282R
Delay time, SDTACK low in the first DIO access to the SIF register
to SDTACK low in the immediately following access to the SIF
Delay time, SIACK high to SDTACK in the high-impedance state
Delay time, SDBEN low to SDTACK low in a read cycle
Delay time, SIACK low to SDBEN low (see TMS380 Second
Generation Token-Ring User’s Guide, SPWU005, subsection
3.4.1.1.1) provided the previous cycle completed
0
4000
0
tc(SCK)
0 tc(SCK) / 2 + 4
0
tc(SCK) + 3
0
4000
ns
0
tc(SCK) ns
0 tc(SCK) / 2 + 4 ns
0
tc(SCK) + 3 ns
283R Delay time, SIACK high to SDBEN high (see Note 24)
0 tc(SCK) / 2 + 4
0 tc(SCK) / 2 + 4 ns
286 Pulse duration, SIACK high between DIO accesses (see Note 24) tc(SCK)
tc(SCK)
ns
† _{This specification is provided as an aid to board design. It is not assured during manufacturing testing.}
‡ _{This specification has been characterized to meet stated value. It is not assured during manufacturing testing.}
§ _{It is the later of SRD and SRD or SCS low that indicates the start of the cycle.}
NOTE 24: The inactive chip select is SIACK in DIO read and DIO write cycles, and SCS is the inactive chip select in interrupt-acknowledge cycles.
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
63