TI380C27 Datasheet, PDF (71/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
68xxx-mode bus arbitration timing, SIF returns control
25-MHz
NO.
OPERATION
MIN MAX
220†
Delay time, SBCLK low in I1 cycle to SAD, SPL, SPH, SUDS, and SLDS in the
high-impedance state, bus release
35
223b† Delay time, SBCLK low in I1 cycle to SBHE/SRNW in the high-impedance state
45
224b Delay time, SBCLK low in cycle I2 to SOWN high
0
20
224d Delay time, SBCLK low in cycle I2 to SDDIR high
27
230 Delay time, SBCLK high to either SHRQ low or SBRQ high
20
240†
Setup from, SUDS, SLDS, SRNW, and SAS control signals in the high-impedance state
before SOWN no longer low
0
† _{This specification has been characterized to meet stated value. It is not assured during manufacturing testing.}
33-MHz
OPERATION
MIN MAX
35
45
0
15
22
15
0
UNIT
ns
ns
ns
ns
ns
ns
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71