TI380C27 Datasheet, PDF (42/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
ethernet timing of XMIT signals: TXD
NO.
305 tXDHLD Hold time, TXD after TXC high
306 tXDVLD Delay time, TXC high to TXD valid and TXC high to TXEN high
MIN MAX UNIT
5
ns
40 ns
TXC
TXD
TXEN
305
306
306
Figure 15. Ethernet Timing of XMIT Signals: TXD
2.4 V
0.45 V
2.4 V
0.45 V
ethernet timing of RCV signals: start of frame
NO.
MIN TYP MAX UNIT
310 RXDSET Setup time, RXD before RXC no longer low
20
ns
311 RXDHLD Hold time, RXD after RXC high
5
ns
312 CRSSET Setup time, CRS high before RXC no longer low for first valid data sample
20
ns
313 SAMDLY Delay time, CRS internally recognized to first valid data sample (see Notes 19 and 20)
clock
3
cycles
314 RXCHI Pulse duration, RXC high
36
ns
315 RXCL0 Pulse duration, RXC low
36
ns
NOTES: 19. For valid frame synchronization, one of the following data sequences must be received. Any other pattern delays frame
synchronization until after the next CRS rising edge.
a) 0 followed by n occurrences of 10 followed by 11, where n is on integer ≥ 3. For example, if n = 3, the data sequence is
010101011.
b) 10 followed by n occurrences of 10 followed by 11, where n is an integer ≥ 3. For example, if n = 3, the data sequence is
1010101011.
20. If a previous frame or frame fragment is completed without extra RXC clock cycles (XTRCVC = 0), SAMDLY = 2 clock cycles.
312
CRS
313
314
RXC
315
RXD
311
310
Figure 16. Ethernet Timing of RCV Signals: Start Of Frame
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