TI380C27 Datasheet, PDF (4/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
description (continued)
The TI380C27 has a bus interface to the host system, a bus interface to local memory, and an interface to the
physical-layer circuitry. Pin names starting with the letter S attach to the host-system bus and pin names starting
with the letter M attach to the local-memory bus. Active-low signals have names with overbars; e.g., SCS.
functional block diagram
SADH0
SADH7
SADL0
SADL7
SPH
SPL
SBRLS
SINTR/SIRQ
SDDIR
SDBEN
SALE
SXAL
SOWN
SIACK
SBCLK
SRD/SUDS
SWR/SLDS
SRDY/SDTACK
SI/M
SHLDA/SBGR
SBHE/SRNW
SRAS/SAS
S8/SHALT
SRESET
SRS0
SRS1
SRS2/SBERR
SCS
SRSX
SHRQ/SBRQ
SBBSY
BTSTRP
PRTYEN
NSELOUT0
NSELOUT1
System
Interface
(SIF)
• DIO Control
• Bus Control
• DMA Control
Memory
Interface
(MIF)
• DRAM Refresh
• Local-Bus
Arbitrator
• Local-Bus
Control
• Local
Parity-Check /
Generator
Clock
Generator
(CG)
Communications
Processor
Adapter-
Support
Function
(ASF)
• Interrupts
• Test Function
RCLK / RXC
REDY / CRS
WFLT / COLL
RCVR / RXD
PXTALIN / TXC
Protocol Handler (PH)
for Token-Ring and
Ethernet Interface
MADH0
MADH7
MADL0
MADL7
MRAS
MCAS
MAXPH
MAXPL
MW
MOE
MDDIR
MAL
MAX0
MAX2
MRESET
MROMEN
MBEN
MBRQ
MBGR
MACS
MBIAEN
MREF
OSCIN
OSCOUT
MBCLK1
MBCLK2
SYNCIN
CLKDIV
NMI
EXTINT0
EXTINT3
TEST0
TEST5
XMATCH
XFAIL
FRAQ / TXD
NSRT / LPBK
WRAP / TXEN
DRVR
DRVR
4
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