TI380C27 Datasheet, PDF (65/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
68xxx-mode bus-arbitration timing, SIF takes control
25-MHz
33-MHz
NO.
OPERATION
OPERATION
MIN
MAX MIN
MAX
208a
Setup time, asynchronous input SBGR before SBCLK no longer high to
assure recognition on this cycle
10
10
Hold time, asynchronous input SBGR after SBCLK low to assure
208b _{recognition on this cycle}
10
10
212 Delay time, SBCLK low to address valid
0
20
0
20
224a Delay time, SBCLK low in cycle I2 to SOWN low (see Note 27)
0
20
0
15
224c Delay time, SBCLK low in cycle I2 to SDDIR low in DMA read
28
23
230 Delay time, SBCLK high to either SHRQ low or SBRQ high
20
15
241 Delay time, SBCLK high in TX cycle to SUDS and SLDS high
25
25
241a†
Hold time, SUDS, SLDS, SRNW, and SAS in the high-impedance state
after SOWN low, bus acquisition
tc(SCK) _{– 15}
tc(SCK) _{– 15}
† _{This specification has been characterized to meet stated value. It is not assured during manufacturing testing.}
NOTE 27: Motorola-style bus slaves hold SDTACK active until the bus master deasserts SAS.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
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