TI380C27 Datasheet, PDF (28/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
timing parameters
The timing parameters for all the signals of TI380C27 are shown in the following tables and are illustrated in
the accompanying figures. The purpose of these figures and tables is to quantify the timing relationships among
the various signals. The parameters are numbered for convenience.
static signals
The following table lists signals that are not allowed to change dynamically and therefore have no timing
associated with them. They should be strapped high, low, or left unconnected as required.
SIGNAL
FUNCTION
SI/M
Host-processor select (Intel/Motorola)
CLKDIV
Reserved
BTSTRP
Default bootstrap mode (RAM/ROM)
PRTYEN
Default parity select (enabled/disabled)
TEST0
Test terminal indicates network type
TEST1
Test terminal indicates network type
TEST2
Test terminal indicates network type
TEST3
Test terminal for TI manufacturing test ^†
TEST4
Test terminal for TI manufacturing test ^†
TEST5
Test terminal for TI manufacturing test ^†
† _{For unit-in-place test}
timing parameter symbology
Some timing parameter symbols have been created in accordance with JEDEC Standard 100-A. In order to
shorten the symbols, some of the signal names and other related terminology have been abbreviated as shown
below:
DR
DRN
OSC
SCK
DRVR
DRVR
OSCIN
SBCLK
Lower case subscripts are defined as follows:
RS
VDD
SRESET
VDDL, VDD
c
cycle time
d
delay time
h
hold time
w
pulse duration (width)
r
rise time
sk
skew
su
setup time
t
transition time
The following additional letters and phrases are defined as follows:
H
High
L
Low
V
Valid
Z
Falling edge
Rising edge
High impedance
No longer high
No longer low
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