TI380C27 Datasheet, PDF (24/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
SIF adapter-control register (SIFACL) (continued)
Bit 5:
SWDDIR — Current SDDIR Signal Value
This bit contains the current value of the pseudo-DMA direction. This enables the host to easily
determine the direction of DMA transfers, which allows system DMA to be controlled by system
software.
0 = Pseudo DMA from host system to TI380C27
1 = Pseudo DMA from TI380C27 to host system
Bit 6:
SWHRQ — Current SHRQ Signal Value
This bit contains the current value on SHRQ/SBRQ when in Intel mode, and the inverse of the
value on SHRQ/SBRQ in Motorola mode. This enables the host to easily determine if a
pseudo-DMA transfer is requested.
INTEL MODE (SI/M = H)
0 = System bus not requested
1 = System bus requested
MOTOROLA MODE (SI/M = L)
System bus not requested
System bus requested
Bit 7:
Bit 8:
Bit 9:
Bit 10:
PSDMAEN — Pseudo-System-DMA Enable
This bit enables pseudo-DMA operation.
0 = Normal bus-master DMA operation is possible.
1 = Pseudo-DMA operation selected. Operation dependent on the values of SWHLDA and
SWHRQ bits in the SIFACL register.
ARESET — Adapter Reset
This bit is a hardware reset of the TI380C27. This bit has the same effect as SRESET except
that the DIO interface to the SIFACL register is maintained. This bit is set to 1 if a clock failure
is detected (OSCIN, PXTALIN, RCLK, or SBCLK not valid).
0 = The TI380C27 operates normally.
1 = The TI380C27 is held in the reset condition.
CPHALT — Communications-Processor Halt
This bit controls TI380C27’s processor access to the internal TI380C27 buses. This prevents the
TI380C27 from executing instructions before the microcode has been downloaded.
0 = The TI380C27 processor can access the internal TI380C27 buses.
1 = The TI380C27 processor is prevented from accessing the internal adapter buses.
BOOT — Bootstrap CP Code
This bit indicates whether the memory in chapters 0 and 31 of the local-memory space is RAM
or ROM/PROM/EPROM. This bit controls the operation of MCAS and MROMEN.
0 = ROM/PROM/EPROM memory in chapters 0 and 31
1 = RAM memory in chapters 0 and 31
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