TI380C27 Datasheet, PDF (64/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
SCS, SRSX,
SRS0, SRS1,
SBHE
Only SCS needs to be Inactive.
All others are don’t care.
267
SIACK
SRNW
272a
SLDS
286
273a
SDDIR
High
282R
283R
286
279
SDBEN
SDTACK
(see Note A)
SADH0 – SADH7,
SADL0 – SADL7,
SPH, SPL
(see Note B)
276
Hi-Z
259
Hi-Z
282a
260
275
255
Output Data Valid
261
261a
Hi-Z
Hi-Z
NOTES: A. SDTACK is an active-low bus ready signal. It must be asserted before data output.
B. Internal logic drives SDTACK high and verifies that it has reached a valid high level before making it a 3-state signal.
Figure 32. 68xxx Interrupt-Acknowledge-Cycle Timing
64
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