TI380C27 Datasheet, PDF (43/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
ethernet timing of RCV signals: end of frame
NO.
MIN TYP MAX UNIT
Setup time, CRS low before RXC no longer low to determine if last data bit seen on
320 CRSSET _{previous RXC no longer low (see Note 21)}
20
ns
321
CRSHLD
Hold time, CRS low after RXC no longer low to determine if last data bit seen on
previous RXC no longer low
0
ns
322 XTRCYC Number of extra RXC clock cycles after last data bit (CRS is low) (see Note 21)
0
5
cycle
NOTE 21: The TI380C27 operates correctly even with no extra RXC clock cycles, provided that CRS does not remain asserted longer than
2 µs (see timing spec NORXC). Provided no extra clocks affect receive-startup timing, see timing spec SAMDLY.
RXC
CRS
320
321
322
RXD
Last
Data Bit
Figure 17. Ethernet Timing of RCV Signals: End of Frame
ethernet timing of RCV signals: no RXC
NO.
330 NORXC Time with no clock pulse on RXC, when CRS is high (see Note 22)
NOTE 22: If NORXC is exceeded, local-clock-failure circuitry may become activated, resetting the device.
CRS
(high)
RXC
330
Figure 18. Ethernet Timing of RCV Signals: No RXC
MIN MAX UNIT
2 µs
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