TI380C27 Datasheet, PDF (12/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
PIN
NAME
NO.
SRSX
47
SRS0
46
SRS1
45
SRS2/SBERR
54
SWR/SLDS
61
SXAL
63
SYNCIN
136
I/O ^†
I
I/O
O
I
Pin Functions (Continued)
DESCRIPTION
Intel Mode
SRSX and SRS0 – SRS2 are used for system-register select. These inputs select the
word or byte to be transferred during a system DIO access. The most significant bit is
SRSX and the least significant bit is SRS2 (see Note 1).
MSb
Register selected = SRSX
SRS0
SRS1
LSb
SRS2/SBERR
SRSX, SRS0 and SRS1 are used for system-register select. These inputs select the
word or byte to be transferred during a system DIO access. The most significant bit is
SRSX and the least significant bit is SRS1 (see Note 1).
Motorola
Mode
MSb
Register selected = SRSX
SRS0
LSb
SRS1
SBERR is used for bus error. SBERR corresponds to the bus-error signal of the 68xxx
microprocessor. SBERR is internally synchronized to SBCLK. This input is driven low
during a DMA cycle to indicate to the TI380C27 that the cycle must be terminated, (see
Section 3.4.5.3 of the TMS380 Second-Generation Token Ring User’s Guide
(SPWU005) for more information).
SWR is used for system-write strobe (see Note 7). SWR is an active-low write strobe that
is an input during DIO and an output during DMA.
Intel Mode
H = Write cycle is not occurring.
L = If DMA, data to be driven from SIF to host bus.
If DIO, on the rising edge, the data is latched and written to the selected register.
Motorola
Mode
SLDS is used for lower-data strobe (see Note 7). SLDS is an input during DIO and an
output during DMA.
H = Not valid data on SADL0 – SADL7 lines
L = Valid data on SADL0 – SADL7 lines
System-extended-address latch. SXAL provides the enable pulse used to externally latch the most
significant 16 bits of the 32-bit system address during DMA. SXAL is activated prior to the first cycle
of each block DMA transfer, and thereafter as necessary (whenever an increment of the DMA address
counter causes a carry out of the lower 16 bits). Systems that implement parity on addresses can use
SXAL to externally latch the parity bits (available on SPL and SPH) for the DMA address extension.
Reserved. SYNCIN must be left unconnected (see Note 1).
Intel Mode
S8 is used for system 8/16-bit bus select. S8 selects the bus width used for
communications through the system interface. On the rising edge of SRESET, the
TI380C27 latches the DMA bus width; otherwise, the value on S8 dynamically selects
the DIO bus width.
S8/SHALT
51
I
H = Selects 8-bit mode (see Note 1)
L = Selects 16-bit mode
SHALT is used for system halt/bus error retry. If SHALT is asserted along with SBERR,
Motorola
Mode
the adapter retries the last DMA cycle. This is the rerun operation as defined in the 68xxx
specification. The BERETRY counter is not decremented by SBERR when SHALT is
asserted (see Section 3.4.5.3 of the TMS380 Second-Generation Token Ring User’s
Guide (SPWU005) for more information).
† _{I = input, O = output}
NOTES: 1. Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
7. Pin should be tied to VCC with a 4.7-kΩ pullup resistor.
12
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443