TI380C27 Datasheet, PDF (8/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
PIN
NAME
NO.
MW
142
NMI
33
OSCIN
135
Pin Functions (Continued)
I/O ^†
O
I
I
DESCRIPTION
Local-memory write. MW is used to specify a write cycle on the local-memory bus. The data on the
MADH0 – MADH7 and MADL0 – MADL7 buses is valid while MW is low. DRAMs latch data on the falling
edge of MW, while SRAMs latch data on the rising edge of MW.
H = Not a local-memory write cycle
L = Local-memory write cycle
Nonmaskable interrupt request. NMI must be left unconnected.
External oscillator input. OSCIN provides the clock frequency to the TI380C27 for a 4-MHz or 6-MHz
internal bus (see Note 5 and Note 6).
CLKDIV
H
L
OSCIN
64 MHz for a 4-MHz local bus
32 MHz for a 4-MHz local bus or 48 MHz for a 6-MHz local bus
Oscillator output
OSCOUT
122
O
CLKDIV
L
OSCOUT
OSCIN / 4 (if OSCIN = 32 MHz, OSCOUT = 8 MHz; if OSCIN = 48 MHz,
OSCOUT = 12 MHz
H
OSCIN / 8 (if OSCIN = 64 MHz, then OSCOUT = 8 MHz)
PRTYEN
Parity enable. The value on PRTYEN is loaded into the PEN bit of the SIFACL register at reset (i.e.,
when SRESET is asserted or the ARESET bit in the SIFACL register is set) to form a default value.
41
I
PRTYEN enables parity checking for the local memory.
H = Local-memory data bus checked for parity (see Note 1)
L = Local-memory data bus not checked for parity
Network selection outputs. NSELOUT0 and NSELOUT1 are controlled by the host through the
corresponding bits of the SIFACL register. The value of these bits/signals can be changed only while
the TI380C27 is reset.
NSELOUT0
NSELOUT1
40
119
O
NSELOUT0
L
L
H
H
NSELOUT1
L
H
L
H
DESCRIPTION
Full-duplex Ethernet
16-Mbps token ring
Half-duplex Ethernet
4-Mbps token ring
SADH0
SADH1
SADH2
SADH3
SADH4
SADH5
SADH6
SADH7
97
System address/data bus — high byte (see Note 1).These lines make up the most significant byte of
96
each address word (32-bit address bus) and data word (16-bit data bus). The most significant bit is
95
SADH0, and the least significant bit is SADH7.
94
93
I/O
Address multiplexing: Bits 31 – 24 and bits 15 – 8
92
Data multiplexing: Bits 15 – 8
86
85
SADL0
76
System address/data bus — low byte (see Note 1). These lines make up the least significant byte of
SADL1
75
each address word (32-bit address bus) and data word (16-bit data bus). The most significant bit is
SADL2
74
SADL0, and the least significant bit is SADL7.
SADL3
SADL4
70
69
I/O
Address multiplexing: Bits 23 – 16 and bits 7 – 0
SADL5
68
Data multiplexing : Bits 7 – 0
SADL6
67
SADL7
66
† _{I = input, O = output}
NOTES: 1 Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch or loads).
5. Pin has an expanded input voltage specification.
6. A maximum of two TI380C27 devices may be connected to any one oscillator.
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