TI380C27 Datasheet, PDF (17/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
architecture
The major blocks of the TI380C27 include the communications processor (CP), system interface (SIF), memory
interface (MIF), protocol handler (PH), clock generator (CG), and adapter support function (ASF). The
functionality of each block is described in the following sections.
communications processor (CP)
The CP performs the control and monitoring of the other functional blocks in the TI380C27. The control and
monitoring protocols are specified by the software (downloaded or ROM based) in local memory. Available
protocols include:
• Media access control (MAC) software
• Logical link control (LLC) software (token-ring mode only)
• Copy all frames (CAF) software
The CP is a proprietary 16-bit central processing unit (CPU) with data cache and a single prefetch pipe for
pipelining of instructions. These features enhance the TI380C27’s maximum performance capability to about
8 million instructions per second (MIPS), with an average of about 5 MIPS.
system interface (SIF)
The SIF performs the interfacing of the LAN subsystem to the host system. This interface may require additional
logic depending on the application. The system interface can transfer information/data using any of these three
methods:
• Direct memory access (DMA)
• Direct input / output (DIO)
• Pseudo-direct memory access (PDMA)
DMA (or PDMA) is used to transfer all data to/from host memory from/to local memory. The main uses of DIO
are for loading the software to local memory and for initializing the TI380C27. DIO also allows command/status
interrupts to occur to and from the TI380C27.
The system interface can be hardware selected for either of two modes by use of SI/M. The mode selected
determines the memory organizations and control signals used. These modes are:
• The Intel 80x8x families: 8-, 16-, and 32-bit bus devices
• The Motorola 68xxx microprocessor family: 16- and 32-bit bus devices
The system interface supports host-system memory addressing up to 32 bits (32-bit reach into the host-system
memory). This allows greater flexibility in using/accessing host-system memory. System designers are allowed
to customize the system interface to their particular bus by:
• Programmable burst transfers or cycle-steal DMA operations
• Optional parity protection
These features are implemented in hardware to reduce system overhead, facilitate automatic rearbitration of
the bus after a burst, or repeat a cycle when errors occur (parity or bus). Bus retries are also supported.
The system-interface hardware also includes features to enhance the integrity of the TI380C27 and the data.
These features include the following:
• Always internally maintain odd-byte parity regardless of parity being disabled
• Monitor for the presence of a clock failure
• Switchable SIF speeds of 2 MHz to 33 MHz
On every cycle, the system interface compares all the system clocks to a reference clock. If any of the clocks
become invalid, the TI380C27 enters the slow-clock mode, which prevents latch-up of the TI380C27. If the
SBCLK is invalid, any DMA cycle is terminated immediately; otherwise, the DMA cycle is completed and the
TI380C27 is placed in the slow-clock mode.
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