TI380C27 Datasheet, PDF (68/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

SBCLK
SAS
(see Note A)
SUDS,
SLDS
SRNW
T4
High
216
TX
218
T1
S1
S2
TWAIT
V
T2
T3
S3
S4
S5
S6
T4
S7
222
210
239
223R
217
217
T1
209
209
SXAL
216
218
216a
SALE
SADL0 – SADH7,
SADH0 – SADL7,
SPH, SPL
SDTACK
(see Notes B and C)
SDDIR
212
233
233
Extended Address
212
233a
Address
214
See Note D
247
208a
208b
205
Data In
229
206
207a
Hi-Z
207b
SDBEN
(see Note A)
237R
225R
NOTES: A. Motorola-style bus slaves hold SDTACK active until the bus master deasserts SAS.
B. All VSS pins should be routed to minimize inductance to system ground.
C. On a read cycle, the read strobe remains active until the internal sample of incoming data is completed. Input data can be removed when either the read strobe or SDBEN
becomes no longer active.
D. If parameter 208a is not met, valid data must be present before SDTACK goes low.
Figure 34. 68xxx-Mode DMA Read-Cycle Timing