TI380C27 Datasheet, PDF (5/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
PIN
NAME
NO.
BTSTRP
42
I/O ^†
I
Pin Functions
DESCRIPTION
Bootstrap. The value on BTSTRP is loaded into the BOOT bit of the SIFACL register at reset (i.e., when
SRESET is asserted or the ARESET bit in the SIFACL register is set) to form a default value. BTSTRP
indicates whether chapters 0 and 31 of the memory map are RAM or ROM. If these chapters are RAM,
the TI380C27 is denied access to the local-memory bus until the CPHALT bit in the SIFACL register
is cleared.
CLKDIV
EXTINT0
EXTINT1
EXTINT2
EXTINT3
MACS
MADH0
MADH1
MADH2
MADH3
MADH4
MADH5
MADH6
MADH7
MADL0
MADL1
MADL2
MADL3
MADL4
MADL5
MADL6
MADL7
MAL
H = Chapters 0 and 31 of local memory are RAM based (see Note 1).
L = Chapters 0 and 31 of local memory are ROM based.
Clock divider select (see Note 2)
38
I
H = 64-MHz OSCIN for 4-MHz local bus
L = 32-MHz OSCIN for 4-MHz local bus or 48-MHz OSCIN for 6-MHz local bus
32
31
30
I/O
Reserved; must be pulled high (see Note 3)
29
132
I
Reserved; must be tied low (see Note 4)
15
Local-memory address, data, and status bus — high byte. For the first quarter of the local-memory
14
cycle, these bus lines carry address bits AX4 and A0 to A6; for the second quarter, they carry status
13
bits; and for the third and fourth quarters, they carry data bits 0 to 7. The most significant bit is MADH0
12
8
I/O
and the least significant bit is MADH7.
7
Memory Cycle
6
1Q
2Q
3Q
4Q
5
Signal
AX4, A0 – A6 Status
D0 – D7
D0 – D7
28
Local-memory address, data, and status bus — low byte. For the first quarter of the local-memory
27
cycle, these bus lines carry address bits A7 to A14; for the second quarter, they carry address bits AX4
26
and A0 to A6; and for the third and fourth quarters, they carry data bits 8 to 15. The most significant
25
24
I/O
bit is MADL0 and the least significant bit is MADL7.
23
Memory Cycle
22
1Q
2Q
3Q
4Q
21
Signal
A7 – A14 AX4, A0 – A6 D8 – D15
D8 – D15
Memory-address latch. MAL is a strobe signal for sampling the address at the start of the memory
cycle; it is used by SRAMs and EPROMs. The full 20-bit word address is valid on MAX0, MAXPH,
MAX2, MAXPL, MADH0 – MADH7, and MADL0 – MADL7. Three 8-bit transparent latches can be used
131
O
to retain a 20-bit static address throughout the cycle.
Rising edge = No signal latching
Falling edge = Allows the above address signals to be latched
Local-memory-extended address bit. MAX0 drives AX0 at row-address time and drives A12 at
column-address and data-valid times for all cycles. This signal can be latched by MRAS. Driving A12
MAX0
eases interfacing to a BIA ROM.
139
I/O
Memory Cycle
1Q
2Q
3Q
4Q
Signal
AX0
A12
A12
A12
† _{I = input, O = output}
NOTES: 1. Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
2. The TI380FPA and TMS380SRA are currently supported only with the 4-MHz local bus in either CLKDIV state. Expansion to support
the 6-MHz local bus is under development.
3. Each pin must be individually tied to VCC with a 1-kΩ pullup resistor.
4. Pin should be connected to ground.
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