LAN9303 Datasheet, PDF (99/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
In full-duplex mode, the PHY is able to transmit and receive data simultaneously. In this mode, CRS
responds only to receive activity. The CSMA/CD protocol does not apply and collision detection is
disabled.
7.2.6 HP Auto-MDIX
HP Auto-MDIX facilitates the use of CAT-3 (10 BASE-T) or CAT-5 (100 BASE-T) media UTP
interconnect cable without consideration of interface wiring scheme. If a user plugs in either a direct
connect LAN cable or a cross-over patch cable, as shown in Figure 7.4 (See Note 7.1 on page 89),
the PHY is capable of configuring the TXPx/TXNx and RXPx/RXNx twisted pair pins for correct
transceiver operation.
The internal logic of the device detects the TX and RX pins of the connecting device. Since the RX
and TX line pairs are interchangeable, special PCB design considerations are needed to accommodate
the symmetrical magnetics and termination of an Auto-MDIX design.
The Auto-MDIX function can be disabled through the Auto-MDIX Control (AMDIXCTRL) bit of the Port
x PHY Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x). When
Auto-MDIX Control (AMDIXCTRL) is cleared, Auto-MDIX can be selected via the Auto-MDIX Enable
configuration straps (auto_mdix_strap_1 and auto_mdix_strap_2 for Port 1 and Port 2, respectively).
The MDIX can also be configured manually via the Manual MDIX strap (manual_mdix_strap_1 and
manual_mdix_strap_2 for Port 1 and Port 2, respectively) if both the Auto-MDIX Control (AMDIXCTRL)
bit and the Auto-MDIX Enable configuration strap are low. Refer to Section 3.2, "Pin Descriptions," on
page 24 for more information on the configuration straps.
When the Auto-MDIX Control (AMDIXCTRL) bit of the Port x PHY Special Control/Status Indication
Register (PHY_SPECIAL_CONTROL_STAT_IND_x) is set to 1, the Auto-MDIX capability is determined
by the Auto-MDIX Enable (AMDIXEN) and Auto-MDIX State (AMDIXSTATE) bits of the Port x PHY
Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x).
7.2.7
RJ-45 8-pin straight-through
for 10BASE-T/100BASE-TX
signaling
TXPx 1
TXNx 2
RXPx 3
Not Used 4
Not Used 5
RXNx 6
Not Used 7
Not Used 8
1 TXPx
2 TXNx
3 RXPx
4 Not Used
5 Not Used
6 RXNx
7 Not Used
8 Not Used
Direct Connect Cable
RJ-45 8-pin cross-over for
10BASE-T/100BASE-TX
signaling
TXPx 1
TXNx 2
RXPx 3
Not Used 4
Not Used 5
RXNx 6
Not Used 7
Not Used 8
1 TXPx
2 TXNx
3 RXPx
4 Not Used
5 Not Used
6 RXNx
7 Not Used
8 Not Used
Cross-Over Cable
Figure 7.4 Direct Cable Connection vs. Cross-Over Cable Connection
MII MAC Interface
The MII MAC Interface is responsible for the transmission and reception of the Ethernet data to and
from the Switch Fabric MAC. The PHY is connected internally to the Switch Fabric MAC via standard
MII signals per IEEE 802.3.
For a transmission, the Switch Fabric MAC drives the transmit data onto the internal MII TXD bus and
asserts TXEN to indicate valid data. The data is in the form of 4-bit wide data at a rate of 25MHz for
100BASE-TX, or 2.5MHz for 10BASE-T.
SMSC LAN9303/LAN9303i
99
DATASHEET
Revision 1.3 (08-27-09)