LAN9303 Datasheet, PDF (123/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
and a high selects the internal 50MHz clock. The high setting also enables P0_OUTCLK as an output
to be used as the system reference clock.
9.1.3.2
Clock Drive Strength
When P0_OUTCLK is configured as an output via the RMII Clock Direction bit of the Virtual PHY
Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS), its drive strength is based on
the setting of the RMII/Turbo MII Clock Strength bit of the Virtual PHY Special Control/Status Register
(VPHY_SPECIAL_CONTROL_STATUS). A low selects 12ma, a high selects 16ma.
9.1.3.3
Signal Quality Error (SQE) Heartbeat Test
The SQE_HEARTBEAT signal is not generated when operating in RMII PHY mode. The SQEOFF bit
of the Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS) has no
effect when operating in RMII PHY mode.
9.1.3.4
Collision Test
External MAC collision testing is not available when operating in the RMII PHY mode. The Collision
Test (VPHY_COL_TEST) bit of the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) has no
effect on system operation in RMII PHY mode.
Switch Engine collision testing is available and is enabled when the Switch Collision Test Port 0 bit of
the Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS) is set. In this
test mode, any transmissions from the Switch Engine will result in the assertion of an internal collision
signal to the Switch Fabric Port 0. Switch Engine collision test occurs regardless of the setting of the
Isolate (VPHY_ISO) bit.
9.1.3.5
Loopback Mode
Two forms of loopback testing are available: External MAC loopback and Switch Engine loopback.
External MAC loopback is enabled when the Loopback (VPHY_LOOPBACK) bit of the Virtual PHY
Basic Control Register (VPHY_BASIC_CTRL) is set. Transmissions from the external MAC are not
sent to the Switch Engine. Instead, they are looped back onto the receive path. Transmissions from
the Switch Engine are ignored.
Switch Engine loopback is enabled when the Switch Looopback Port 0 bit of the Virtual PHY Special
Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS) is set. Transmissions from the Switch
Engine are not sent to the external MAC. Instead, they are looped back internally onto the receive
path. Transmissions from the external MAC are ignored. An internal collision signal to the Switch
Engine is available and is asserted when the Switch Collision Test Port 0 bit is set. Switch Engine
loopback occurs regardless of the setting of the Isolate (VPHY_ISO) bit.
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SMSC LAN9303/LAN9303i
123
DATASHEET
Revision 1.3 (08-27-09)