LAN9303 Datasheet, PDF (101/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
7.2.9.1
PHY General Power-Down
This power-down mode is controlled by the Power Down (PHY_PWR_DWN) bit of the Port x PHY
Basic Control Register (PHY_BASIC_CONTROL_x). In this mode the entire PHY, except the PHY
management control interface, is powered down. The PHY will remain in this power-down state as long
as the bit is set. When the bit is cleared, the PHY powers up and is automatically reset.
7.2.9.2
PHY Energy Detect Power-Down
This power-down mode is enabled by setting the Energy Detect Power-Down (EDPWRDOWN) bit of
the Port x PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x). When in this
mode, if no energy is detected on the line, the entire PHY is powered down except for the PHY
management control interface, the SQUELCH circuit, and the ENERGYON logic. The ENERGYON
logic is used to detect the presence of valid energy from 100BASE-TX, 10BASE-T, or auto-negotiation
signals and is responsible for driving the ENERGYON signal, whose state is reflected in the Energy
On (ENERGYON) bit of the Port x PHY Mode Control/Status Register
(PHY_MODE_CONTROL_STATUS_x).
In this mode, when the ENERGYON signal is cleared, the PHY is powered down and no data is
transmitted from the PHY. When energy is received, via link pulses or packets, the ENERGYON signal
goes high, and the PHY powers up. The PHY automatically resets itself into its previous state prior to
power-down, and asserts the INT7 interrupt bit of the Port x PHY Interrupt Source Flags Register
(PHY_INTERRUPT_SOURCE_x). The first and possibly second packet to activate ENERGYON may
be lost.
When the Energy Detect Power-Down (EDPWRDOWN) bit of the Port x PHY Mode Control/Status
Register (PHY_MODE_CONTROL_STATUS_x) is low, energy detect power-down is disabled.
7.2.10 PHY Resets
In addition to the chip-level hardware reset (nRST) and Power-On Reset (POR), the PHY supports
three block specific resets. These are discussed in the following sections. For detailed information on
all resets and the reset sequence refer to Section 4.2, "Resets," on page 42.
Note:
The Digital Reset (DIGITAL_RST) bit in the Reset Control Register (RESET_CTL) does not
reset the PHYs. Only a hardware reset (nRST) or an EEPROM RELOAD command will
automatically reload the configuration strap values into the PHY registers. For all other PHY
resets, these values will need to be manually configured via software.
7.2.10.1
PHY Software Reset via RESET_CTL
The PHY can be reset via the Reset Control Register (RESET_CTL). The Port 1 PHY is reset by
setting the Port 1 PHY Reset (PHY1_RST) bit, and the Port 2 PHY is reset by setting the Port 2 PHY
Reset (PHY2_RST) bit. These bits are self clearing after approximately 102uS. This reset does not
reload the configuration strap values into the PHY registers.
7.2.10.2
PHY Software Reset via PHY_BASIC_CTRL_x
The PHY can also be reset by setting the Reset (PHY_RST) bit of the Port x PHY Basic Control
Register (PHY_BASIC_CONTROL_x). This bit is self clearing and will return to 0 after the reset is
complete. This reset does not reload the configuration strap values into the PHY registers.
7.2.10.3
PHY Power-Down Reset
After the PHY has returned from a power-down state, a reset of the PHY is automatically generated.
The PHY power-down modes do not reload or reset the PHY registers. Refer to Section 7.2.9, "PHY
Power-Down Modes," on page 100 for additional information.
SMSC LAN9303/LAN9303i
101
DATASHEET
Revision 1.3 (08-27-09)