LAN9303 Datasheet, PDF (117/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
8.4.6
8.4.7
8.5
Note: The starting address is a DWORD address. Appending two 0 bits will form the register address.
As an example, the following is a 3 burst sequence, with 1, 2, and 3 DWORDs starting at register
addresses 40h, 80h, and C0h respectively:
A5h, (Burst Sequence Valid Flag)
3h, (number_of_bursts)
16{10h, 1h}, (starting_address1 divided by 4 / count1)
11h, 12h, 13h, 14h, (4 x count1 of data)
16{20h, 2h}, (starting_address2 divided by 4 / count2)
21h, 22h, 23h, 24h, 25h, 26h, 27h, 28h, (4 x count2 of data)
16{30h, 3h}, (starting_address3 divided by 4 / count3)
31h, 32h, 33h, 34h, 35h, 36h, 37h, 38h, 39h, 3Ah, 3Bh, 3Ch (4 x count3 of data)
In order to avoid overwriting the Switch CSR register interface or the PHY Management Interface
(PMI), the EEPROM Loader waits until the CSR Busy (CSR_BUSY) bit of the Switch Fabric CSR
Interface Command Register (SWITCH_CSR_CMD) and the MII Busy (MIIBZY) bit of the PHY
Management Interface Access Register (PMI_ACCESS) are cleared before performing any register
write.
The EEPROM Loader checks that the EEPROM address space is not exceeded. If so, it will stop and
set the EEPROM Loader Address Overflow (LOADER_OVERFLOW) bit in the EEPROM Command
Register (E2P_CMD). The address limit is based on the eeprom_size_strap which specifies a range
of sizes. The address limit is set to the largest value of the specified range.
EEPROM Loader Finished Wait-State
Once finished with the last burst, the EEPROM Loader will go into a wait-state and the EEPROM
Controller Busy (EPC_BUSY) bit of the EEPROM Command Register (E2P_CMD) will be cleared.
Reset Sequence and EEPROM Loader
In order to allow the EEPROM Loader to change the Port 1/2 PHYs and Virtual PHY strap inputs and
maintain consistency with the PHY and Virtual PHY registers, the following sequence is used:
1. After power-up or upon a hardware reset (nRST), the straps are sampled into the device as
specified in Section 14.5.2, "Reset and Configuration Strap Timing," on page 351.
2. After the PLL is stable, the main chip reset is released and the EEPROM Loader reads the
EEPROM and configures (overrides) the strap inputs.
3. The EEPROM Loader writes select Port 1/2 and Virtual PHY registers, as specified in
Section 8.4.4.1 and Section 8.4.4.2, respectively.
Note: Step 3 is also performed in the case of a RELOAD command or digital reset.
I²C Slave Operation
When in MAC/PHY I²C managed mode, the I²C slave interface is used for CPU management of the
device. All system CSRs are accessible to the CPU in these modes. I²C mode is selected when the
mngt_mode_strap[1:0] configuration straps are set to 10b, respectively. The I²C slave controller
implements the low level I²C slave serial interface (start and stop condition detection, data bit
transmission and reception, and acknowledge generation and reception), handles the slave command
protocol, and performs system register reads and writes. The I²C slave controller conforms to the NXP
I²C-Bus Specification.
SMSC LAN9303/LAN9303i
117
DATASHEET
Revision 1.3 (08-27-09)