LAN9303 Datasheet, PDF (225/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
13.4.1.3 Switch Global Interrupt Mask Register (SW_IMR)
Register #:
0004h
Size:
32 bits
This read/write register contains the global interrupt mask for the Switch Fabric interrupts. All switch
related interrupts in the Switch Global Interrupt Pending Register (SW_IPR) may be masked via this
register. An interrupt is masked by setting the corresponding bit of this register. Clearing a bit will
unmask the interrupt. When an unmasked Switch Fabric interrupt is generated in the Switch Global
Interrupt Pending Register (SW_IPR), the interrupt will trigger the Switch Fabric Interrupt Event
(SWITCH_INT) bit in the Interrupt Status Register (INT_STS). Refer to Chapter 5, "System Interrupts,"
on page 55 for more information.
BITS
DESCRIPTION
31:9 RESERVED
8:7 RESERVED
Note: These bits must be written as 11b
6 Buffer Manager Interrupt Mask (BM)
When set, prevents the generation of Switch Fabric interrupts due to the
Buffer Manager via the Buffer Manager Interrupt Pending Register
(BM_IPR). The status bits in the Switch Global Interrupt Pending Register
(SW_IPR) register are not affected.
5 Switch Engine Interrupt Mask (SWE)
When set, prevents the generation of Switch Fabric interrupts due to the
Switch Engine via the Switch Engine Interrupt Pending Register (SWE_IPR).
The status bits in the Switch Global Interrupt Pending Register (SW_IPR)
register are not affected.
4:3 RESERVED
Note: These bits must be written as 11b
2 Port 2 MAC Interrupt Mask (MAC_2)
When set, prevents the generation of Switch Fabric interrupts due to the
Port 2 MAC via the MAC_IPR_2 register (see Section 13.4.2.44, on
page 270). The status bits in the Switch Global Interrupt Pending Register
(SW_IPR) register are not affected.
1 Port 1 MAC Interrupt Mask (MAC_1)
When set, prevents the generation of Switch Fabric interrupts due to the
Port 1 MAC via the MAC_IPR_1 register (see Section 13.4.2.44, on
page 270). The status bits in the Switch Global Interrupt Pending Register
(SW_IPR) register are not affected.
0 Port 0 MAC Interrupt Mask (MAC_0)
When set, prevents the generation of Switch Fabric interrupts due to the
Port 0 MAC via the MAC_IPR_0 register (see Section 13.4.2.44, on
page 270). The status bits in the Switch Global Interrupt Pending Register
(SW_IPR) register are not affected.
TYPE
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DEFAULT
-
11b
1b
1b
11b
1b
1b
1b
SMSC LAN9303/LAN9303i
225
DATASHEET
Revision 1.3 (08-27-09)