LAN9303 Datasheet, PDF (122/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
9.1.2.4
Collision Test
Two forms of collision testing are available: External MAC collision testing and Switch Engine collision
testing.
External MAC collision testing is enabled when the Collision Test (VPHY_COL_TEST) bit of the Virtual
PHY Basic Control Register (VPHY_BASIC_CTRL) is set. In this test mode, any transmissions from
the external MAC will result in collision signaling to the external MAC via the P0_COL pin.
Switch Engine collision testing is enabled when the Switch Collision Test Port 0 bit of the Virtual PHY
Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS) is set. In this test mode, any
transmissions from the Switch Engine will result in the assertion of the internal collision signal to the
Switch Fabric Port 0. Switch Engine collision testing occurs regardless of the setting of the Isolate
(VPHY_ISO) bit.
9.1.2.5
Loopback
Two forms of loopback testing are available: External MAC loopback and Switch Engine loopback.
External MAC loopback is enabled when the Loopback (VPHY_LOOPBACK) bit of the Virtual PHY
Basic Control Register (VPHY_BASIC_CTRL) is set. Transmissions from the external MAC are not
sent to the Switch Engine and are not used for purposes of signaling data valid, collision or carrier
sense to the Switch Engine. Instead, they are looped back onto the receive path. Transmissions from
the Switch Engine are ignored and are not used for purposes of signaling data valid, collision or carrier
sense on the MII pins. The collision output to the external MAC (via P0_COL) is not generated unless
the Collision Test (VPHY_COL_TEST) bit is set. The SQE_HEARTBEAT signal does not drive the
collision output (via P0_COL) during External MAC loopback but can drive it during Switch Engine
loopback. The carrier sense output on the P0_CRS pin is only based on the transmit enable from the
external MAC (via the P0_INDV pin).
Switch Engine loopback is enabled when the Switch Looopback Port 0 bit of the Virtual PHY Special
Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS) is set. Transmissions from the Switch
Engine are not sent to the external MAC and are not used for purposes of signaling data valid, collision
or carrier sense to the MII pins. Instead, they are looped back internally onto the receive path.
Transmissions from the external MAC are ignored and are not used for purposes of data valid, collision
or carrier sense to the Switch Engine. The collision signal to the Switch Engine is not generated unless
the Switch Collision Test Port 0 bit is set. The carrier sense signal is only based on the transmit enable
from the Switch Engine. Switch Engine loopback occurs regardless of the setting of the Isolate
(VPHY_ISO) bit.
9.1.3 Port 0 RMII PHY Mode
Port 0 RMII PHY mode is used when interfacing Port 0 to an external MAC that does not support the
full MII interface. The RMII interface uses a subset of the MII pins. The P0_OUTD[1:0], P0_OUTDV,
P0_IND[1:0], P0_INDV, and P0_OUTCLK pins are the only MII pins used to communicate with the
external MAC in this mode. This mode provides collision testing for the Switch Engine, as well as
loopback test capabilities.
Note: The RMII standard does not support external MAC collision testing.
When in RMII PHY mode, if the Isolate (VPHY_ISO) bit of the Virtual PHY Basic Control Register
(VPHY_BASIC_CTRL) is set, MII data path output pins are three-stated, the pull-ups and pull-downs
are disabled and the MII data path input pins are ignored (disabled into the non-active state and
powered down). Note that setting the Isolate (VPHY_ISO) bit does not cause isolation of the MII
management pins and does not affect MII MAC mode.
9.1.3.1
Reference Clock Selection
The 50MHz RMII reference clock can be selected from either the P0_OUTCLK pin input or the internal
50MHz clock. The choice is based on the setting of the RMII Clock Direction bit of the Virtual PHY
Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS). A low selects P0_OUTCLK
Revision 1.3 (08-27-09)
122
DATASHEET
SMSC LAN9303/LAN9303i