LAN9303 Datasheet, PDF (100/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
For reception, the 4-bit data nibbles are sent to the MII MAC Interface block. These data nibbles are
clocked to the controller at a rate of 25MHz for 100BASE-TX, or 2.5MHz for 10BASE-T. RXCLK is the
output clock for the internal MII bus. It is recovered from the received data to clock the RXD bus. If
there is no received signal, it is derived from the system reference clock.
7.2.8 PHY Management Control
The PHY Management Control block is responsible for the management functions of the PHY,
including register access and interrupt generation. A Serial Management Interface (SMI) is used to
support registers 0 through 6 as required by the IEEE 802.3 (Clause 22), as well as the vendor specific
registers allowed by the specification. The SMI interface consists of the MII Management Data (MDIO)
signal and the MII Management Clock (MDC) signal. These signals interface to the MDIO and MDC
pins of LAN9303/LAN9303i (or the PMI block in I²C mode of operation) and allow access to all PHY
registers. Refer to Section 13.3.2, "Port 1 & 2 PHY Registers," on page 191 for a list of all supported
registers and register descriptions. Non-supported registers will be read as FFFFh.
7.2.8.1
PHY Interrupts
The PHY contains the ability to generate various interrupt events as described in Table 7.3. Reading
the Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x) shows the source of
the interrupt, and clears the interrupt signal. The Port x PHY Interrupt Mask Register
(PHY_INTERRUPT_MASK_x) enables or disables each PHY interrupt. The PHY Management Control
block aggregates the enabled interrupts status into an internal signal which is sent to the System
Interrupt Controller and is reflected via the Interrupt Status Register (INT_STS) bits Port 1 PHY
Interrupt Event (PHY_INT1) and Port 2 PHY Interrupt Event (PHY_INT2) for the Port 1 and Port 2
PHYs, respectively. For more information on interrupts, refer to Chapter 5, "System Interrupts," on
page 55.
Table 7.3 PHY Interrupt Sources
INTERRUPT SOURCE
ENERGYON Activated
Auto-Negotiation Complete
Remote Fault Detected
Link Down (Link Status Negated)
Auto-Negotiation LP Acknowledge
Parallel Detection Fault
Auto-Negotiation Page Received
PHY_INTERRUPT_MASK_x &
PHY_INTERRUPT_SOURCE_x REGISTER BIT #
7
6
5
4
3
2
1
7.2.9 PHY Power-Down Modes
There are two power-down modes for the PHY:
„ PHY General Power-Down
„ PHY Energy Detect Power-Down
Note: For more information on the various power management features of the device, refer to Section
4.3, "Power Management," on page 54.
Note: The power-down modes of each PHY (Port 1 PHY and Port 2 PHY) are controlled
independently.
Note: The PHY power-down modes do not reload or reset the PHY registers.
Revision 1.3 (08-27-09)
100
DATASHEET
SMSC LAN9303/LAN9303i