LAN9303 Datasheet, PDF (47/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
STRAP NAME
LED_en_strap[5:0]
LED_fun_strap[1:0]
auto_mdix_strap_1
manual_mdix_strap_1
Table 4.2 Soft-Strap Configuration Strap Definitions
DESCRIPTION
PIN / DEFAULT
VALUE
LED Enable Straps: Configures the default value for the 1b
LED Enable 5-0 (LED_EN[5:0]) bits of the LED
Configuration Register (LED_CFG).
LED Function Straps: Configures the default value for the 00b
LED Function 1-0 (LED_FUN[1:0]) bits of the LED
Configuration Register (LED_CFG).
Port 1 Auto-MDIX Enable Strap: Configures the default
value of the AMDIX_EN Strap State Port 1 bit of the
Hardware Configuration Register (HW_CFG).
AMDIX1_LED0P
Note 4.1
This strap is also used in conjunction with
manual_mdix_strap_1 to configure Port 1 Auto-MDIX
functionality when the Auto-MDIX Control (AMDIXCTRL) bit
in the (x=1) Port x PHY Special Control/Status Indication
Register (PHY_SPECIAL_CONTROL_STAT_IND_x)
indicates the strap settings should be used for auto-MDIX
configuration.
Refer to the respective register definition sections for
additional information.
Port 1 Manual MDIX Strap: Configures MDI(0) or MDIX(1) 0b
for Port 1 when the auto_mdix_strap_1 is low and the Auto-
MDIX Control (AMDIXCTRL) bit of the (x=1) Port x PHY
Special Control/Status Indication Register
(PHY_SPECIAL_CONTROL_STAT_IND_x) indicates the
strap settings are to be used for auto-MDIX configuration.
autoneg_strap_1
Port 1 Auto Negotiation Enable Strap: Configures the 1b
default value of the Auto-Negotiation (PHY_AN) enable bit
of the (x=1) Port x PHY Basic Control Register
(PHY_BASIC_CONTROL_x).
This strap also may affect the default value of the following
register bits (x=1):
„ Speed Select LSB (PHY_SPEED_SEL_LSB) and Duplex
Mode (PHY_DUPLEX) bits of the Port x PHY Basic
Control Register (PHY_BASIC_CONTROL_x)
„ 10BASE-T Full Duplex and 10BASE-T Half Duplex bits of
the Port x PHY Auto-Negotiation Advertisement Register
(PHY_AN_ADV_x)
„ PHY Mode (MODE[2:0]) bits of the Port x PHY Special
Modes Register (PHY_SPECIAL_MODES_x)
Refer to the respective register definition sections for
additional information.
SMSC LAN9303/LAN9303i
47
DATASHEET
Revision 1.3 (08-27-09)