LAN9303 Datasheet, PDF (27/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
Table 3.4 Port 0 MII/RMII Pins (continued)
NUM
PINS
NAME
SYMBOL
1
Port 0 MII Input
Error
P0_INER
Port 0 MII Input
1
Reference
Clock
P0_INCLK
Port 0 MII
Output Data 3
P0_OUTD3
1
Port 0 Duplex
Polarity
Configuration
Strap
DUPLEX_POL_0
BUFFER
TYPE
DESCRIPTION
IS
(PD)
MII MAC Mode: This pin is the RX_ER signal from
the external PHY and indicates a receive error in
the packet.
IS
(PD)
MII PHY Mode: This pin is the TX_ER signal from
the external MAC and indicates that the current
packet should be aborted. The pull-down and input
buffer are disabled when the Isolate (VPHY_ISO)
bit is set in the Virtual PHY Basic Control Register
(VPHY_BASIC_CTRL).
-
RMII PHY Mode: This pin is not used.
IS
(PD)
MII MAC Mode: This pin is an input and is used as
the reference clock for the P0_IND[3:0], P0_INER,
and P0_INDV pins. It is connected to the receive
clock of the external PHY.
O12/O16
MII PHY Mode: This pin is an output and is used
as the reference clock for the P0_IND[3:0],
P0_INER, and P0_INDV pins. It is connected to the
transmit clock of the external MAC. The output
driver is disabled when the Isolate (VPHY_ISO) bit
is set in the Virtual PHY Basic Control Register
(VPHY_BASIC_CTRL). When operating at
200MBps, the choice of drive strength is based on
the setting of the RMII/Turbo MII Clock Strength bit
in the Virtual PHY Special Control/Status Register
(VPHY_SPECIAL_CONTROL_STATUS). A low
selects a 12 mA drive, while a high selects a 16 mA
drive. A series terminating resistor is recommended
for the best PCB signal integrity.
-
RMII PHY Mode: This pin is not used.
O8
MII MAC Mode: This pin is the transmit data 3 bit
from the switch to the external PHY.
O8
MII PHY Mode: This pin is the receive data 3 bit
from the switch to the external MAC. The output
driver is disabled when the Isolate (VPHY_ISO) bit
is set in the Virtual PHY Basic Control Register
(VPHY_BASIC_CTRL).
-
RMII PHY Mode: This pin is not used
IS
(PU)
Note 3.5
This strap selects the default of the duplex polarity
strap for Port 0 MII (duplex_pol_strap_0). See
Note 3.4.
If the strap is value is 0, a 0 on P0_DUPLEX
means full duplex while a 1 means half duplex. If
the strap value is 1, a 1 on P0_DUPLEX means full
duplex, while a 0 means half duplex.
SMSC LAN9303/LAN9303i
27
DATASHEET
Revision 1.3 (08-27-09)