LAN9303 Datasheet, PDF (43/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
Table 4.1 Reset Sources and Affected Device Circuitry
RESET SOURCE
POR X
X
X
X
X
X
X
X
X
X
X
nRST Pin X
X
X
X
X
X
X
X
X
X
X
Digital Reset X
X
X
X
X
X
X
X
X
Port 2 PHY
X
Port 1 PHY
X
Virtual PHY
X
4.2.1
4.2.1.1
4.2.1.2
Chip-Level Resets
A chip-level reset event activates all internal resets, effectively resetting the entire device. Configuration
straps are latched, and the EEPROM Loader is run as a result of chip-level resets. A chip-level reset
is initiated by assertion of any of the following input events:
„ Power-On Reset (POR)
„ nRST Pin Reset
Chip-level reset/configuration completion can be determined by first polling the Byte Order Test
Register (BYTE_TEST). The returned data will be invalid until the serial interface resets are complete.
Once the returned data is the correct byte ordering value, the serial interface resets have completed.
The completion of the entire chip-level reset must then be determined by polling the Device Ready
(READY) bit of the Hardware Configuration Register (HW_CFG) until it is set. When set, the Device
Ready (READY) bit indicates that the reset has completed and the device is ready to be accessed.
With the exception of the Hardware Configuration Register (HW_CFG), Byte Order Test Register
(BYTE_TEST), and Reset Control Register (RESET_CTL), read access to any internal resources is
forbidden while the Device Ready (READY) bit is cleared. Writes to any address are invalid until the
Device Ready (READY) bit is set.
Power-On Reset (POR)
A power-on reset occurs whenever power is initially applied to the device, or if the power is removed
and reapplied to the device. This event resets all circuitry within the device. Configuration straps are
latched, and the EEPROM Loader is run as a result of this reset.
A POR reset typically takes approximately 23mS, plus an additional 91uS per byte of data loaded from
the EEPROM via the EEPROM Loader. A full EEPROM load of 64KB will complete in approximately
6.0 seconds.
nRST Pin Reset
Driving the nRST input pin low initiates a chip-level reset. This event resets all circuitry within the
device. Use of this reset input is optional, but when used, it must be driven for the period of time
specified in Section 14.5.2, "Reset and Configuration Strap Timing," on page 351. Configuration straps
are latched, and the EEPROM Loader is run as a result of this reset.
SMSC LAN9303/LAN9303i
43
DATASHEET
Revision 1.3 (08-27-09)