LAN9303 Datasheet, PDF (45/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
In addition to the methods above, the Port 2 PHY is automatically reset after returning from a PHY
power-down mode. This reset differs in that the PHY power-down mode reset does not reload or reset
any of the PHY registers. Refer to Section 7.2.9, "PHY Power-Down Modes," on page 100 for
additional information.
Port 2 PHY reset completion can be determined by polling the Port 2 PHY Reset (PHY2_RST) bit in
the Reset Control Register (RESET_CTL) or the Reset (PHY_RST) bit in the (x=2) Port x PHY Basic
Control Register (PHY_BASIC_CONTROL_x) until it clears. Under normal conditions, these bits will
clear approximately 110uS after the Port 2 PHY reset occurrence.
Note: When using the Reset (PHY_RST) bit to reset the Port 2 PHY, register bits designated as
NASR are not reset.
Refer to Section 7.2.10, "PHY Resets," on page 101 for additional information on Port 2 PHY resets.
4.2.3.2
Port 1 PHY Reset
A Port 1 PHY reset is performed by setting the Port 1 PHY Reset (PHY1_RST) bit of the Reset Control
Register (RESET_CTL) or the Reset (PHY_RST) bit in the (x=1) Port x PHY Basic Control Register
(PHY_BASIC_CONTROL_x). Upon completion of the Port 1 PHY reset, the Port 1 PHY Reset
(PHY1_RST) and Reset (PHY_RST) bits are automatically cleared. No other modules of the device
are affected by this reset.
In addition to the methods above, the Port 1 PHY is automatically reset after returning from a PHY
power-down mode. This reset differs in that the PHY power-down mode reset does not reload or reset
any of the PHY registers. Refer to Section 7.2.9, "PHY Power-Down Modes," on page 100 for
additional information.
Port 1 PHY reset completion can be determined by polling the Port 1 PHY Reset (PHY1_RST) bit in
the Reset Control Register (RESET_CTL) or the Reset (PHY_RST) bit in the (x=1) Port x PHY Basic
Control Register (PHY_BASIC_CONTROL_x) until it clears. Under normal conditions, these bits will
clear approximately 110uS after the Port 1 PHY reset occurrence.
Note: When using the Reset (PHY_RST) bit to reset the Port 1 PHY, register bits designated as
NASR are not reset.
Refer to Section 7.2.10, "PHY Resets," on page 101 for additional information on Port 1 PHY resets.
4.2.3.3
Virtual PHY Reset
A Virtual PHY reset is performed by setting the Virtual PHY Reset (VPHY_RST) bit of the Reset
Control Register (RESET_CTL) or Reset (VPHY_RST) in the Virtual PHY Basic Control Register
(VPHY_BASIC_CTRL). No other modules of the device are affected by this reset.
Virtual PHY reset completion can be determined by polling the Virtual PHY Reset (VPHY_RST) bit in
the Reset Control Register (RESET_CTL) or the Reset (VPHY_RST) bit in the Virtual PHY Basic
Control Register (VPHY_BASIC_CTRL) until it clears. Under normal conditions, these bits will clear
approximately 1uS after the Virtual PHY reset occurrence.
Refer to Section 7.3.3, "Virtual PHY Resets," on page 104 for additional information on Virtual PHY
resets.
4.2.4
Configuration Straps
Configuration straps allow various features of the device to be automatically configured to user defined
values. Configuration straps can be organized into two main categories: hard-straps and soft-straps.
Both hard-straps and soft-straps are latched upon Power-On Reset (POR) or pin reset (nRST). The
primary difference between these strap types is that soft-strap default values can be overridden by the
EEPROM Loader, while hard-straps cannot.
Configuration straps which have a corresponding external pin include internal resistors in order to
prevent the signal from floating when unconnected. If a particular configuration strap is connected to
SMSC LAN9303/LAN9303i
45
DATASHEET
Revision 1.3 (08-27-09)