LAN9303 Datasheet, PDF (142/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

13.2.1.2
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
Interrupt Status Register (INT_STS)
Offset:
058h
Size:
32 bits
This register contains the current status of the generated interrupts. A value of 1 indicates the
corresponding interrupt conditions have been met, while a value of 0 indicates the interrupt conditions
have not been met. The bits of this register reflect the status of the interrupt source regardless of
whether the source has been enabled as an interrupt in the Interrupt Enable Register (INT_EN). Where
indicated as R/WC, writing a 1 to the corresponding bits acknowledges and clears the interrupt.
BITS
DESCRIPTION
31
30
29
28
27
26
25:20
19
Software Interrupt (SW_INT)
This interrupt is generated when the Software Interrupt Enable
(SW_INT_EN) bit of the Interrupt Enable Register (INT_EN) is set high.
Writing a one clears this interrupt.
Device Ready (READY)
This interrupt indicates that the device is ready to be accessed after a
power-up or reset condition.
RESERVED
Switch Fabric Interrupt Event (SWITCH_INT)
This bit indicates an interrupt event from the Switch Fabric. This bit should
be used in conjunction with the Switch Global Interrupt Pending Register
(SW_IPR) to determine the source of the interrupt event within the Switch
Fabric.
Port 2 PHY Interrupt Event (PHY_INT2)
This bit indicates an interrupt event from the Port 2 PHY. The source of the
interrupt can be determined by polling the Port x PHY Interrupt Source
Flags Register (PHY_INTERRUPT_SOURCE_x).
Port 1 PHY Interrupt Event (PHY_INT1)
This bit indicates an interrupt event from the Port 1 PHY. The source of the
interrupt can be determined by polling the Port x PHY Interrupt Source
Flags Register (PHY_INTERRUPT_SOURCE_x).
RESERVED
GP Timer (GPT_INT)
This interrupt is issued when the General Purpose Timer Count Register
(GPT_CNT) wraps past zero to FFFFh.
18:13
12
11:0
RESERVED
GPIO Interrupt Event (GPIO)
This bit indicates an interrupt event from the General Purpose I/O. The
source of the interrupt can be determined by polling the General Purpose
I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN)
RESERVED
TYPE
R/WC
R/WC
RO
RO
RO
RO
RO
R/WC
RO
RO
RO
DEFAULT
0b
0b
-
0b
0b
0b
-
0b
-
0b
-
Revision 1.3 (08-27-09)
142
DATASHEET
SMSC LAN9303/LAN9303i