LAN9303 Datasheet, PDF (118/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

8.5.1
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
The I²C slave serial interface consists of a data wire (SDA) and a serial clock (SCL). The serial clock
is driven by the master, while the data wire is bi-directional. Both signals are open-drain and require
external pull-up resistors.
The I²C slave serial interface supports the standard-mode speed of up to 100KHz and the fast-mode
speed of 400KHz. Refer to the NXP I²C-Bus Specification for detailed I²C timing information.
I²C Slave Command Format
The I²C slave serial interface supports single register and multiple register read and write commands.
A read or write command is started by the master first sending a start condition, followed by a control
byte. The control byte consists of a 7-bit slave address and a 1-bit read/write indication (R/~W). The
slave address used by the device is 0001010b, written as SA6 (first bit on the wire) through SA0 (last
bit on the wire). Assuming the slave address in the control byte matches this address, the control byte
is acknowledged by the device. Otherwise, the entire sequence is ignored until the next start condition.
The I²C command format can be seen in Figure 8.8.
If the read/write indication (R/~W) in the control byte is a 0 (indicating a potential write), the next byte
sent by the master is the register address. After the address byte is acknowledged by the device, the
master may either send data bytes to be written, or it may send another start condition (to start the
reading of data), or a stop condition. The latter two will terminate the current write (without writing any
data), but will have the affect of setting the internal register address which will be used for subsequent
reads.
If the read/write indication in the control byte is a 1 (indicating a read), the device will start sending
data following the control byte acknowledgement.
Note: All registers are accessed as DWORDs. Appending two 0 bits to the address field will form the
register address. Addresses and data are transferred msb first. Data is transferred MSB first
(little endian).
Control Byte
Address Byte
S
S
A
6
S
A
5
S
A
4
S
A
3
S
A
2
S
A
1
S
A
0
0
A
C
K
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
C
K
*
R/~W
Start or
Stop or
Data [31]
8.5.2
Figure 8.8 I²C Slave Addressing
I²C Slave Read Sequence
Following the device addressing, as detailed in Section 8.5.1, a register is read from the device when
the master sends a start condition and control byte with the R/~W bit set. Assuming the slave address
in the control byte matches the device address, the control byte is acknowledged by the device.
Otherwise, the entire sequence is ignored until the next start condition. Following the acknowledge,
the device sends 4 bytes of data. The first 3 bytes are acknowledged by the master and on the fourth,
the master sends a no-acknowledge followed by the stop condition. The no-acknowledge informs the
device not to send the next 4 bytes (as it would in the case of a multiple read). The internal register
address is unchanged following the single read.
Multiple reads are performed when the master sends an acknowledge on the fourth byte. The internal
address is incremented and the next register is shifted out. Once the internal address reaches its
maximum, it rolls over to 0. The multiple read is concluded when the master sends a no-acknowledge
followed by a stop condition. The no-acknowledge informs the device not to send the next 4 bytes.
The internal register address in incremented for each read including the final.
Revision 1.3 (08-27-09)
118
DATASHEET
SMSC LAN9303/LAN9303i