LAN9303 Datasheet, PDF (168/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

13.2.5.2
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
PHY Management Interface Access Register (PMI_ACCESS)
Offset:
0A8h
Size:
32 bits
This register is used to control the management cycles to the PHYs. A PHY access is initiated when
this register is written. This register is used in conjunction with the PHY Management Interface Data
Register (PMI_DATA) to perform read and write operations to the PHYs.
Note: The Virtual PHY registers are NOT accessible via these registers.
BITS
DESCRIPTION
31:16 RESERVED
15:11
PHY Address (PHY_ADDR)
These bits select the PHY device being accessed. Refer to Section 7.1.1,
"PHY Addressing," on page 88 for information on PHY address
assignments.
10:6 MII Register Index (MIIRINDA)
These bits select the desired MII register in the PHY. Refer to Section 13.3,
"Ethernet PHY Control and Status Registers," on page 191 for detailed
descriptions on all PHY registers.
5:2 RESERVED
1 MII Write (MIIWnR)
Setting this bit informs the PHY that the access will be a write operation
using the PHY Management Interface Data Register (PMI_DATA). If this bit
is cleared, the access will be a read operation, returning data into the PHY
Management Interface Data Register (PMI_DATA).
0 MII Busy (MIIBZY)
This bit must be read as 0 before writing to the PHY Management Interface
Data Register (PMI_DATA) or PHY Management Interface Access Register
(PMI_ACCESS) registers. This bit is automatically set when this register is
written. During a PHY register access, this bit will be set, signifying a read
or write access is in progress. This is a self-clearing (SC) bit that will return
to 0 when the PHY register access has completed.
During a PHY register write, the PHY Management Interface Data Register
(PMI_DATA) must be kept valid until this bit is cleared.
During a PHY register read, the PHY Management Interface Data Register
(PMI_DATA) register is invalid until the MAC has cleared this bit.
TYPE
RO
R/W
R/W
RO
R/W
RO
SC
DEFAULT
-
00000b
00000b
-
0b
0b
Revision 1.3 (08-27-09)
168
DATASHEET
SMSC LAN9303/LAN9303i