LAN9303 Datasheet, PDF (131/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
Chapter 11 General Purpose Timer & Free-Running Clock
11.1
11.2
This chapter details the General Purpose Timer (GPT) and the Free-Running Clock.
General Purpose Timer
The device provides a 16-bit programmable General Purpose Timer that can be used to generate
periodic system interrupts. The resolution of this timer is 100uS.
The GPT loads the General Purpose Timer Count Register (GPT_CNT) with the value in the General
Purpose Timer Pre-Load (GPT_LOAD) field of the General Purpose Timer Configuration Register
(GPT_CFG) when the General Purpose Timer Enable (TIMER_EN) bit of the General Purpose Timer
Configuration Register (GPT_CFG) is asserted (1). On a chip-level reset, or when the General Purpose
Timer Enable (TIMER_EN) bit changes from asserted (1) to de-asserted (0), the General Purpose
Timer Pre-Load (GPT_LOAD) field is initialized to FFFFh. The General Purpose Timer Count Register
(GPT_CNT) is also initialized to FFFFh on reset. Software can write a pre-load value into the General
Purpose Timer Pre-Load (GPT_LOAD) field at any time (e.g. before or after the General Purpose Timer
Enable (TIMER_EN) bit is asserted).
Once enabled, the GPT counts down until it reaches 0000h, or until a new pre-load value is written to
the General Purpose Timer Pre-Load (GPT_LOAD) field. At 0000h, the counter wraps around to
FFFFh, asserts the GP Timer (GPT_INT) interrupt status bit in the Interrupt Status Register (INT_STS),
asserts the IRQ interrupt (if GP Timer Interrupt Enable (GPT_INT_EN) is set in the Interrupt Status
Register (INT_STS)), and continues counting. GP Timer (GPT_INT) is a sticky bit. Once this bit is
asserted, it can only be cleared by writing a 1 to the bit. Refer to Section 5.2.4, "General Purpose
Timer Interrupt," on page 58 for additional information on the GPT interrupt.
Free-Running Clock
The Free-Running Clock (FRC) is a simple 32-bit up-counter that operates from a fixed 25MHz clock.
The current FRC value can be read via the Free Running 25MHz Counter Register (FREE_RUN). On
assertion of a chip-level reset, this counter is cleared to zero. On de-assertion of a reset, the counter
is incremented once for every 25MHz clock cycle. When the maximum count has been reached, the
counter rolls over to zeros. The FRC does not generate interrupts.
Note: The free running counter can take up to 160nS to clear after a reset event.
SMSC LAN9303/LAN9303i
131
DATASHEET
Revision 1.3 (08-27-09)