LAN9303 Datasheet, PDF (48/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

STRAP NAME
speed_strap_1
duplex_strap_1
BP_EN_strap_1
FD_FC_strap_1
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
Table 4.2 Soft-Strap Configuration Strap Definitions (continued)
DESCRIPTION
PIN / DEFAULT
VALUE
Port 1 Speed Select Strap:
1b
This strap may affect the default value of the following
register bits (x=1):
„ Speed Select LSB (PHY_SPEED_SEL_LSB) bit of the
Port x PHY Basic Control Register
(PHY_BASIC_CONTROL_x)
„ PHY Mode (MODE[2:0]) bits of the Port x PHY Special
Modes Register (PHY_SPECIAL_MODES_x)
„ 10BASE-T Full Duplex and 10BASE-T Half Duplex bits of
the Port x PHY Auto-Negotiation Advertisement Register
(PHY_AN_ADV_x)
Refer to the respective register definition sections for
additional information.
Port 1 Duplex Select Strap: This strap affects the default 1b
value of the following register bits (x=1):
„ Duplex Mode (PHY_DUPLEX) bit of the Port x PHY Basic
Control Register (PHY_BASIC_CONTROL_x)
„ PHY Mode (MODE[2:0]) bits of the Port x PHY Special
Modes Register (PHY_SPECIAL_MODES_x)
„ 10BASE-T Full Duplex bit of the Port x PHY Auto-
Negotiation Advertisement Register (PHY_AN_ADV_x)
Refer to the respective register definition sections for
additional information.
Port 1 Backpressure Enable Strap: Configures the
1b
default value for the Port 1 Backpressure Enable
(BP_EN_1) bit of the Port 1 Manual Flow Control Register
(MANUAL_FC_1).
Port 1 Full-Duplex Flow Control Enable Strap: This strap 1b
is used to configure the default value of the following
register bits (x=1):
„ Port 1 Full-Duplex Transmit Flow Control Enable
(TX_FC_1) and Port 1 Full-Duplex Receive Flow Control
Enable (RX_FC_1) bits of the Port 1 Manual Flow Control
Register (MANUAL_FC_1)
This strap may affect the default value of the following
register bits (x=1):
„ Asymmetric Pause bit of the Port x PHY Auto-Negotiation
Advertisement Register (PHY_AN_ADV_x)
Refer to the respective register definition sections for
additional information.
Revision 1.3 (08-27-09)
48
DATASHEET
SMSC LAN9303/LAN9303i