LAN9303 Datasheet, PDF (167/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
13.2.5 PHY Management Interface (PMI)
The PMI registers are used to indirectly access the PHY registers. Refer to Section 13.3, "Ethernet
PHY Control and Status Registers," on page 191 for additional information on the PHY registers. Refer
to Section 10.3, "PHY Management Interface (PMI)," on page 126 for information on the PMI.
Note: The Virtual PHY registers are NOT accessible via these registers.
13.2.5.1 PHY Management Interface Data Register (PMI_DATA)
Offset:
0A4h
Size:
32 bits
This register is used in conjunction with the PHY Management Interface Access Register
(PMI_ACCESS) to perform read and write operations to the PHYs.
Note: The Virtual PHY registers are NOT accessible via these registers.
BITS
DESCRIPTION
31:16 RESERVED
15:0 MII Data
This field contains the value read from or written to the PHYs. For a write
operation, this register should be first written with the desired data. For a
read operation, the PMI_ACCESS register is first written and once the
command is finished, this register will contain the return data.
Note:
Upon a read, the value returned depends on the MII Write
(MIIWnR) bit in the PHY Management Interface Access Register
(PMI_ACCESS). If MII Write (MIIWnR) is 0, the data is from the
PHY. If MII Write (MIIWnR) is 1, the data is the value that was last
written into this register.
TYPE
RO
R/W
DEFAULT
-
0000h
SMSC LAN9303/LAN9303i
167
DATASHEET
Revision 1.3 (08-27-09)