LAN9303 Datasheet, PDF (49/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
Table 4.2 Soft-Strap Configuration Strap Definitions (continued)
STRAP NAME
manual_FC_strap_1
DESCRIPTION
PIN / DEFAULT
VALUE
Port 1 Manual Flow Control Enable Strap: Configures the 0b
default value of the Port 1 Full-Duplex Manual Flow Control
Select (MANUAL_FC_1) bit in the Port 1 Manual Flow
Control Register (MANUAL_FC_1).
This strap affects the default value of the following register
bits (x=1):
„ Asymmetric Pause and Symmetric Pause bits of the Port
x PHY Auto-Negotiation Advertisement Register
(PHY_AN_ADV_x)
auto_mdix_strap_2
manual_mdix_strap_2
autoneg_strap_2
Port 2 Auto-MDIX Enable Strap: Configures the default
value of the AMDIX_EN Strap State Port 2 bit of the
Hardware Configuration Register (HW_CFG).
AMDIX2 LED1P
Note 4.1
This strap is used in conjunction with manual_mdix_strap_2
to configure Port 2 Auto-MDIX functionality when the Auto-
MDIX Control (AMDIXCTRL) bit in the (x=2) Port x PHY
Special Control/Status Indication Register
(PHY_SPECIAL_CONTROL_STAT_IND_x) indicates the
strap settings should be used for auto-MDIX configuration.
Refer to the respective register definition sections for
additional information.
Port 2 Manual MDIX Strap: Configures MDI(0) or MDIX(1) 0b
for Port 2 when the auto_mdix_strap_2 is low and the Auto-
MDIX Control (AMDIXCTRL) bit of the (x=2) Port x PHY
Special Control/Status Indication Register
(PHY_SPECIAL_CONTROL_STAT_IND_x) indicates the
strap settings are to be used for auto-MDIX configuration.
Port 2 Auto Negotiation Enable Strap: Configures the 1b
default value of the Auto-Negotiation (PHY_AN) enable bit
in the (x=2) Port x PHY Basic Control Register
(PHY_BASIC_CONTROL_x).
This strap may also affect the default value of the following
register bits (x=2):
„ Speed Select LSB (PHY_SPEED_SEL_LSB) and Duplex
Mode (PHY_DUPLEX) bits of the Port x PHY Basic
Control Register (PHY_BASIC_CONTROL_x)
„ 10BASE-T Full Duplex and 10BASE-T Half Duplex bits of
the Port x PHY Auto-Negotiation Advertisement Register
(PHY_AN_ADV_x)
„ PHY Mode (MODE[2:0]) bits of the Port x PHY Special
Modes Register (PHY_SPECIAL_MODES_x)
Refer to the respective register definition sections for
additional information.
SMSC LAN9303/LAN9303i
49
DATASHEET
Revision 1.3 (08-27-09)