LAN9303 Datasheet, PDF (51/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
Table 4.2 Soft-Strap Configuration Strap Definitions (continued)
STRAP NAME
manual_FC_strap_2
speed_strap_0
duplex_pol_strap_0
BP_EN_strap_0
FD_FC_strap_0
DESCRIPTION
PIN / DEFAULT
VALUE
Port 2 Manual Flow Control Enable Strap: Configures the 0b
default value of the Port 2 Full-Duplex Manual Flow Control
Select (MANUAL_FC_2) bit in the Port 2 Manual Flow
Control Register (MANUAL_FC_2).
This strap affects the default value of the following register
bits (x=2):
„ Asymmetric Pause and Symmetric Pause bits of the Port
x PHY Auto-Negotiation Advertisement Register
(PHY_AN_ADV_x).
Port 0 (External MII) Speed Select Strap: This strap
1b
affects the default value of the following bits in the Virtual
PHY Auto-Negotiation Link Partner Base Page Ability
Register (VPHY_AN_LP_BASE_ABILITY):
„ 100BASE-X Full Duplex
„ 100BASE-X Half Duplex
„ 10BASE-T Full Duplex
„ 10BASE-T Half Duplex
Refer to Section 13.2.6.6 and Table 13.7 for more
information.
This strap also configures the speed for Port 0 when Virtual
Auto-Negotiation fails. Refer to Section 7.3.1.1, "Parallel
Detection," on page 103 for additional information.
Port 0 (External MII) Duplex Polarity Strap: This strap
determines the polarity of the P0_DUPLEX pin in MII MAC
mode and affects the default value of the following bits in
the Virtual PHY Auto-Negotiation Link Partner Base Page
Ability Register (VPHY_AN_LP_BASE_ABILITY):
DUPLEX_POL_0
„ 100BASE-X Full Duplex
„ 100BASE-X Half Duplex
„ 10BASE-T Full Duplex
„ 10BASE-T Half Duplex
Refer to Section 13.2.6.6 and Table 13.7 for more
information.
Port 0 (External MII) Backpressure Enable Strap:
1b
Configures the default value of the Port 0 Backpressure
Enable (BP_EN_0) bit of the Port 0 Manual Flow Control
Register (MANUAL_FC_0).
Port 0 (External MII) Full-Duplex Flow Control Enable 1b
Strap: Configures the default value of the Port 0 Transmit
Flow Control Enable (TX_FC_0) and Port 0 Receive Flow
Control Enable (RX_FC_0) bits in the Port 0 Manual Flow
Control Register (MANUAL_FC_0).
This strap affects the default value of the following register
bits:
„ Asymmetric Pause and Pause bits of the Virtual PHY
Auto-Negotiation Link Partner Base Page Ability Register
(VPHY_AN_LP_BASE_ABILITY)
SMSC LAN9303/LAN9303i
51
DATASHEET
Revision 1.3 (08-27-09)