LAN9303 Datasheet, PDF (161/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
13.2.4.6 Switch Fabric MAC Address High Register (SWITCH_MAC_ADDRH)
Offset:
1F0h
Size:
32 bits
This register contains the upper 16-bits of the MAC address used by the switch for Pause frames. This
register is used in conjunction with Switch Fabric MAC Address Low Register
(SWITCH_MAC_ADDRL). The contents of this register are optionally loaded from the EEPROM at
power-on through the EEPROM Loader if a programmed EEPROM is detected. The least significant
byte of this register (bits [7:0]) is loaded from address 05h of the EEPROM. The second byte (bits
[15:8]) is loaded from address 06h of the EEPROM. The Host can update the contents of this field
after the initialization process has completed.
Refer to Section 13.2.4.7, "Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL)" for
information on how this address is loaded by the EEPROM Loader. Section 8.4, "EEPROM Loader,"
on page 113 contains additional details on using the EEPROM Loader.
BITS
DESCRIPTION
31:23 RESERVED
22 DiffPauseAddr
When set, each port may have a unique MAC address.
21:20 Port 2 Physical Address [41:40]
When DiffPauseAddr is set, these bits are used as bits 41 and 40 of the
MAC Address for Port 2.
19:18 Port 1 Physical Address [41:40]
When DiffPauseAddr is set, these bits are used as bits 41 and 40 of the
MAC Address for Port 1.
17:16 Port 0 Physical Address [41:40]
When DiffPauseAddr is set, these bits are used as bits 41 and 40 of the
MAC Address for Port 0.
15:0 Physical Address[47:32]
This field contains the upper 16-bits (47:32) of the physical address of the
Switch Fabric MACs. Bits 41 and 10 are ignored if DiffPauseAddr is set.
TYPE
RO
R/W
R/W
R/W
R/W
R/W
DEFAULT
-
0b
10b
01b
00b
FFFFh
SMSC LAN9303/LAN9303i
161
DATASHEET
Revision 1.3 (08-27-09)