LAN9303 Datasheet, PDF (57/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
5.2.1
Switch Fabric Interrupts
Multiple Switch Fabric interrupt sources are provided in a three-tiered register structure as shown in
Figure 5.1. The top-level Switch Fabric Interrupt Event (SWITCH_INT) bit of the Interrupt Status
Register (INT_STS) provides indication that a Switch Fabric interrupt event occurred in the Switch
Global Interrupt Pending Register (SW_IPR).
The Switch Engine Interrupt Pending Register (SWE_IPR) and Switch Engine Interrupt Mask Register
(SWE_IMR) provide status and enabling/disabling of all Switch Fabric sub-modules interrupts (Buffer
Manager, Switch Engine, and Port 2,1,0 MACs).
The low-level Switch Fabric sub-module interrupt pending and mask registers of the Buffer Manager,
Switch Engine, and Port 2,1,0 MACs provide multiple interrupt sources from their respective sub-
modules. These low-level registers provide the following interrupt sources:
„ Buffer Manager (Buffer Manager Interrupt Mask Register (BM_IMR) and Buffer Manager Interrupt
Pending Register (BM_IPR))
—Status B Pending
—Status A Pending
„ Switch Engine (Switch Engine Interrupt Mask Register (SWE_IMR) and Switch Engine Interrupt
Pending Register (SWE_IPR))
—Interrupt Pending
„ Port 2,1,0 MACs (Port x MAC Interrupt Mask Register (MAC_IMR_x) and Port x MAC Interrupt
Pending Register (MAC_IPR_x))
—No currently supported interrupt sources. These registers are reserved for future use.
In order for a Switch Fabric interrupt event to trigger the external IRQ interrupt pin, the following must
be configured:
„ The desired Switch Fabric sub-module interrupt event must be enabled in the corresponding mask
register (Buffer Manager Interrupt Mask Register (BM_IMR) for the Buffer Manager, Switch Engine
Interrupt Mask Register (SWE_IMR) for the Switch Engine, and/or Port x MAC Interrupt Mask
Register (MAC_IMR_x) for the Port 2,1,0 MACs)
„ The desired Switch Fabric sub-module interrupt event must be enabled in the Switch Global
Interrupt Mask Register (SW_IMR)
„ Switch Fabric Interrupt Event Enable (SWITCH_INT_EN) bit of the Interrupt Enable Register
(INT_EN) must be set
„ IRQ output must be enabled via the IRQ Enable (IRQ_EN) bit of the Interrupt Configuration
Register (IRQ_CFG)
For additional details on the Switch Fabric interrupts, refer to Section 6.6, "Switch Fabric Interrupts,"
on page 87.
5.2.2 Ethernet PHY Interrupts
The Port 1 and Port 2 PHYs each provide a set of identical interrupt sources. The top-level Port 1 PHY
Interrupt Event (PHY_INT1) and Port 2 PHY Interrupt Event (PHY_INT2) bits of the Interrupt Status
Register (INT_STS) provide indication that a PHY interrupt event occurred in the respective Port x PHY
Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x).
Port 1 and Port 2 PHY interrupts are enabled/disabled via their respective Port x PHY Interrupt Mask
Register (PHY_INTERRUPT_MASK_x). The source of a PHY interrupt can be determined and cleared
via the Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x). The Port 1 and
Port 2 PHYs are each capable of generating unique interrupts based on the following events:
„ ENERGYON Activated
„ Auto-Negotiation Complete
„ Remote Fault Detected
„ Link Down (Link Status Negated)
SMSC LAN9303/LAN9303i
57
DATASHEET
Revision 1.3 (08-27-09)