LAN9303 Datasheet, PDF (53/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
Table 4.3 Hard-Strap Configuration Strap Definitions (continued)
STRAP NAME
P0_mode_strap[1:0]
DESCRIPTION
PIN(S)
Port 0 Mode Strap: Configures the default mode of
operation for Port 0.
00 = MII MAC Mode
01 = MII PHY Mode
10 = RMII PHY Mode
11 = RESERVED
These operating modes result from the following mapping:
P0_MODE2 :
P0_MODE1 :
P0_MODE0
P0_MODE[2:0]
000
001, 010, or 011
100, 101, or 110
111
P0_mode_strap[1:0]
00 (MII MAC)
01 (MII PHY)
10 (RMII PHY)
RESERVED
P0_rmii_clock_dir_strap
P0_clock_strength_strap
turbo_mii_enable_strap_0
phy_addr_sel_strap
led_pol_strap[5:0]
Refer to Section 2.3, "Modes of Operation," on page 19 for
additional information on the various modes of the device.
Port 0 RMII Clock Direction Strap: Configures the default
value of the RMII Clock Direction bit of the Virtual PHY
Special Control/Status Register
(VPHY_SPECIAL_CONTROL_STATUS).
P0_MODE1
Port 0 Clock Strength Strap: Configures the default value
of the RMII/Turbo MII Clock Strength bit of the Virtual PHY
Special Control/Status Register
(VPHY_SPECIAL_CONTROL_STATUS).
P0_MODE0
Port 0 Turbo MII Enable Strap: Configures the default
value of the Turbo MII Enable bit of the Virtual PHY Special
Control/Status Register
(VPHY_SPECIAL_CONTROL_STATUS) when in MII PHY
mode.
P0_MODE1
PHY Address Select Strap: Configures the default MII
PHYADDR_LED5P
management address values for the PHYs and Virtual PHY
Note 4.1
as detailed in Section 7.1.1, "PHY Addressing," on page 88.
LED Polarity Strap: Configures the default polarity for
each of the LEDs when they are an open-drain or open-
source output.
0 = The LED is set as active high, since it is assumed
that a LED to ground is used as the pull-down.
1 = The LED is set as active low, since it is assumed
that a LED to VDD is used as the pull-up.
PHYADDR_LED5P :
MNGT1_LED4P :
MNGT0_LED3P :
E2PSIZE_LED2P :
AMDIX2_LED1P :
AMDIX1_LED0P
Note 4.1 This pin has shared strap functionality. Refer to Table 4.4 for details.
SMSC LAN9303/LAN9303i
53
DATASHEET
Revision 1.3 (08-27-09)