LAN9303 Datasheet, PDF (314/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
13.4.3.39 Switch Engine Interrupt Mask Register (SWE_IMR)
Register #:
1880h
Size:
32 bits
This register contains the Switch Engine interrupt mask, which masks the interrupts in the Switch
Engine Interrupt Pending Register (SWE_IPR). All Switch Engine interrupts are masked by setting the
Interrupt Mask bit. Clearing this bit will unmask the interrupts. Refer to Chapter 5, "System Interrupts,"
on page 55 for more information.
BITS
DESCRIPTION
31:1 RESERVED
0 Interrupt Mask
When set, this bit masks interrupts from the Switch Engine. The status bits
in the Switch Engine Interrupt Pending Register (SWE_IPR) are not
affected.
TYPE
RO
R/W
DEFAULT
-
1b
Revision 1.3 (08-27-09)
314
DATASHEET
SMSC LAN9303/LAN9303i