LAN9303 Datasheet, PDF (208/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
Note 13.66 Register bits designated as NASR are reset when the Port x PHY Reset is generated via
the Reset Control Register (RESET_CTL). The NASR designation is only applicable when
the Reset (PHY_RST) bit of the Port x PHY Basic Control Register
(PHY_BASIC_CONTROL_x) is set.
Table 13.12 Auto-MDIX Enable and Auto-MDIX State Bit Functionality
Auto-MDIX Enable
0
0
1
1
Auto-MDIX State
0
1
0
1
MODE
Manual mode, no crossover
Manual mode, crossover
Auto-MDIX mode
RESERVED (do not use this state)
auto_mdix_strap_x
0
0
1
Table 13.13 MDIX Strap Functionality
manual_mdix_strap_x
MODE
0
Manual mode, no crossover
1
Manual mode, crossover
x
Auto-MDIX mode
Revision 1.3 (08-27-09)
208
DATASHEET
SMSC LAN9303/LAN9303i