LAN9303 Datasheet, PDF (116/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

8.4.4.2
8.4.4.3
8.4.5
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
re-runs the Auto-negotiation using the new default values of the Port x PHY Auto-Negotiation
Advertisement Register (PHY_AN_ADV_x) register to determine the new Auto-negotiation results.
Note: Each of these PHY registers is written in its entirety, overwriting any previously changed bits.
Following the writes to the PHY registers, the PMI registers are reset back to their default values.
Virtual PHY Registers Synchronization
Some PHY register defaults are based on configuration straps. In order to maintain consistency
between the updated configuration strap registers and the Virtual PHY registers, the Virtual PHY Auto-
Negotiation Advertisement Register (VPHY_AN_ADV), Virtual PHY Special Control/Status Register
(VPHY_SPECIAL_CONTROL_STATUS), and Virtual PHY Basic Control Register
(VPHY_BASIC_CTRL) are written when the EEPROM Loader is run.
The Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV) is written with the new
defaults as detailed in Section 13.2.6.5, "Virtual PHY Auto-Negotiation Advertisement Register
(VPHY_AN_ADV)," on page 176.
The Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS) is written
with the new defaults as detailed in Section 13.2.6.8, "Virtual PHY Special Control/Status Register
(VPHY_SPECIAL_CONTROL_STATUS)," on page 182.
The Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) is written with the new defaults as
detailed in Section 13.2.6.1, "Virtual PHY Basic Control Register (VPHY_BASIC_CTRL)," on page 170.
Additionally, the Restart Auto-Negotiation (PHY_RST_AN) bit is set in this register. This re-runs the
Auto-negotiation using the new default values of the Virtual PHY Auto-Negotiation Advertisement
Register (VPHY_AN_ADV) register to determine the new Auto-negotiation results.
Note: Each of these VPHY registers is written in its entirety, overwriting any previously changed bits.
LED and Manual Flow Control Register Synchronization
Since the defaults of the LED Configuration Register (LED_CFG), Port 1 Manual Flow Control Register
(MANUAL_FC_1), Port 2 Manual Flow Control Register (MANUAL_FC_2), and Port 0 Manual Flow
Control Register (MANUAL_FC_0) are based on configuration straps, the EEPROM Loader reloads
these registers with their new default values.
Register Data
Optionally following the configuration strap values, the EEPROM data may be formatted to allow
access to the device’s parallel, directly writable registers. Access to indirectly accessible registers (e.g.
Switch Engine registers, etc.) is achievable with an appropriate sequence of writes (at the cost of
EEPROM space).
This data is first preceded with a Burst Sequence Valid Flag (EEPROM byte 12). If this byte has a
value of A5h, the data that follows is recognized as a sequence of bursts. Otherwise, the EEPROM
Loader is finished, will go into a wait state, and clear the EEPROM Controller Busy (EPC_BUSY) bit
in the EEPROM Command Register (E2P_CMD). This can optionally generate an interrupt.
The data at EEPROM byte 13 and above should be formatted in a sequence of bursts. The first byte
is the total number of bursts. Following this is a series of bursts, each consisting of a starting address,
count, and the count x 4 bytes of data. This results in the following formula for formatting register data:
8-bits number_of_bursts
repeat (number_of_bursts)
16-bits {starting_address[9:2] / count[7:0]}
repeat (count)
8-bits data[31:24], 8-bits data[23:16], 8-bits data[15:8], 8-bits data[7:0]
Revision 1.3 (08-27-09)
116
DATASHEET
SMSC LAN9303/LAN9303i