LAN9303 Datasheet, PDF (206/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

13.3.2.9
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x)
Index (decimal): 18
Size:
16 bits
This read/write register is used to control the special modes of the Port x PHY.
Note: This register is re-written by the EEPROM Loader following the release of reset or a RELOAD
command. Refer to Section 8.4, "EEPROM Loader," on page 113 for more information.
BITS
DESCRIPTION
TYPE
15:8 RESERVED
RO
7:5 PHY Mode (MODE[2:0])
R/W
This field reflects the default PHY mode of operation. Refer to Table 13.11 _NASR
for a definition of each mode.
Note 13.63
4:0 PHY Address (PHYADD)
R/W
The PHY Address field determines the MMI address to which the PHY will NASR
respond and is also used for initialization of the cipher (scrambler) key. Each Note 13.63
PHY must have a unique address. Refer to Section 7.1.1, "PHY
Addressing," on page 88 for additional information.
Note: No check is performed to ensure this address is unique from the
other PHY addresses (Port 1 PHY, Port 2 PHY, and Virtual PHY).
DEFAULT
-
Note 13.64
Note 13.65
Note 13.63 Register bits designated as NASR are reset when the Port x PHY Reset is generated via
the Reset Control Register (RESET_CTL). The NASR designation is only applicable when
the Reset (PHY_RST) bit of the Port x PHY Basic Control Register
(PHY_BASIC_CONTROL_x) is set.
Note 13.64 The default value of this field is determined by a combination of the configuration straps
autoneg_strap_x, speed_strap_x, and duplex_strap_x. If the autoneg_strap_x is 1, then
the default MODE[2:0] value is 111b. Else, the default value of this field is determined by
the remaining straps. MODE[2]=0, MODE[1]=(speed_strap_1 for Port 1 PHY,
speed_strap_2 for Port 2 PHY), and MODE[0]=(duplex_strap_1 for Port 1 PHY,
duplex_strap_2 for Port 2 PHY). Configuration strap values are latched upon the de-
assertion of a chip-level reset as described in Section 4.2.4, "Configuration Straps," on
page 45. Refer to Section 4.2.4, "Configuration Straps," on page 45 for strap definitions.
Note 13.65 The default value of this field is determined by the phy_addr_sel_strap configuration strap.
Refer to Section 7.1.1, "PHY Addressing," on page 88 for additional information.
Table 13.11 MODE[2:0] Definitions
MODE[2:0]
MODE DEFINITIONS
000
10BASE-T Half Duplex. Auto-negotiation disabled.
001
10BASE-T Full Duplex. Auto-negotiation disabled.
010
100BASE-TX Half Duplex. Auto-negotiation disabled. CRS is active during Transmit & Receive.
011
100BASE-TX Full Duplex. Auto-negotiation disabled. CRS is active during Receive.
100
RESERVED
101
RESERVED
110
Power Down mode.
111
All capable. Auto-negotiation enabled.
Revision 1.3 (08-27-09)
206
DATASHEET
SMSC LAN9303/LAN9303i