LAN9303 Datasheet, PDF (207/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
13.3.2.10 Port x PHY Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x)
Index (decimal): 27
Size:
16 bits
This read/write register is used to control various options of the Port x PHY.
BITS
DESCRIPTION
TYPE
15 Auto-MDIX Control (AMDIXCTRL)
R/W
This bit is responsible for determining the source of Auto-MDIX control for _NASR
Port x. When set, the Manual MDIX and Auto MDIX straps
Note 13.66
(manual_mdix_strap_1/auto_mdix_strap_1 for Port 1 PHY,
manual_mdix_strap_2/auto_mdix_strap_2 for Port 2 PHY) are overridden,
and Auto-MDIX functions are controlled using the AMDIXEN and
AMDIXSTATE bits of this register. When cleared, Auto-MDIX functionality is
controlled by the Manual MDIX and Auto MDIX straps by default. Refer to
Section 4.2.4, "Configuration Straps," on page 45 for configuration strap
definitions.
0: Port x Auto-MDIX determined by strap inputs (Table 13.13)
1: Port x Auto-MDIX determined by bits AMDIXEN and AMDIXSTATE
bits
Note:
The values of auto_mdix_strap_1 and auto_mdix_strap_2 are
indicated in the AMDIX_EN Strap State Port 1 and the AMDIX_EN
Strap State Port 2 bits of the Hardware Configuration Register
(HW_CFG).
14 Auto-MDIX Enable (AMDIXEN)
When the AMDIXCTRL bit of this register is set, this bit is used in
conjunction with the AMDIXSTATE bit to control the Port x Auto-MDIX
functionality as shown in Table 13.12.
R/W
NASR
Note 13.66
13 Auto-MDIX State (AMDIXSTATE)
When the AMDIXCTRL bit of this register is set, this bit is used in
conjunction with the AMDIXEN bit to control the Port x Auto-MDIX
functionality as shown in Table 13.12.
R/W
NASR
Note 13.66
12 RESERVED
RO
11 SQE Test Disable (SQEOFF)
This bit controls the disabling of the SQE test (Heartbeat). SQE test is
enabled by default.
0: SQE test enabled
1: SQE test disabled
R/W
NASR
Note 13.66
10 Receive PLL Lock Control (VCOOFF_LP)
R/W
This bit controls the locking of the receive PLL. Setting this bit to 1 forces NASR
the receive PLL 10M to lock on the reference clock at all times. When in this Note 13.66
mode, 10M data packets cannot be received.
0: Receive PLL 10M can lock on reference or line as needed (normal
operation)
1: Receive PLL 10M locked onto reference clock at all times
9:5 RESERVED
RO
4 10Base-T Polarity State (XPOL)
RO
This bit shows the polarity state of the 10Base-T.
0: Normal Polarity
1: Reversed Polarity
3:0 RESERVED
RO
DEFAULT
0b
0b
0b
-
0b
0b
-
0b
-
SMSC LAN9303/LAN9303i
207
DATASHEET
Revision 1.3 (08-27-09)