LAN9303 Datasheet, PDF (186/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

13.2.7.3
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
Hardware Configuration Register (HW_CFG)
Offset:
074h
Size:
32 bits
This register allows the configuration of various hardware features.
Note: This register can be polled while the device is in the reset or not ready state (Device Ready
(READY) bit is cleared). Returned data will be invalid during the reset state since the serial
interfaces are also in reset at this time.
Note: In SMI mode, either half of this register can be read without the need to read the other half.
BITS
DESCRIPTION
31:28 RESERVED
27 Device Ready (READY)
When set, this bit indicates that the device is ready to be accessed. Upon
power-up, nRST reset, or digital reset, the host processor may interrogate
this field as an indication that the device has stabilized and is fully active.
This bit can cause an interrupt if enabled.
Note:
With the exception of the HW_CFG, BYTE_TEST, and
RESET_CTL registers, read access to any internal resources is
forbidden while the READY bit is cleared. Writes to any address
are invalid until this bit is set.
26 AMDIX_EN Strap State Port 2
This bit reflects the state of the auto_mdix_strap_2 strap that connects to
the PHY. The strap value is loaded with the level of the auto_mdix_strap_2
during reset and can be re-written by the EEPROM Loader. The strap value
can be overridden by the Auto-MDIX Control (AMDIXCTRL) and Auto-MDIX
State (AMDIXSTATE) bits of the Port 2 PHY Special Control/Status
Indication Register (Section 13.3.2.10).
25 AMDIX_EN Strap State Port 1
This bit reflects the state of the auto_mdix_strap_1 strap that connects to
the PHY. The strap value is loaded with the level of the auto_mdix_strap_1
during reset and can be re-written by the EEPROM Loader. The strap value
can be overridden by the Auto-MDIX Control (AMDIXCTRL) and Auto-MDIX
State (AMDIXSTATE) bits of the Port 1 PHY Special Control/Status
Indication Register (Section 13.3.2.10).
24:0 RESERVED
TYPE
RO
RO
RO
RO
RO
DEFAULT
-
0b
Note 13.53
Note 13.54
-
Note 13.53 The default value of this field is determined by the configuration strap auto_mdix_strap_2.
See Section 4.2.4, "Configuration Straps," on page 45 for more information.
Note 13.54 The default value of this field is determined by the configuration strap auto_mdix_strap_1.
See Section 4.2.4, "Configuration Straps," on page 45 for more information.
Revision 1.3 (08-27-09)
186
DATASHEET
SMSC LAN9303/LAN9303i