LAN9303 Datasheet, PDF (200/366 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
BITS
DESCRIPTION
4:0 Selector Field
This field identifies the type of message being sent by Auto-Negotiation.
00001: IEEE 802.3
TYPE
R/W
DEFAULT
00001b
Note 13.59 The Asymmetric Pause and Symmetric Pause bits are loaded into the PHY registers by
the EEPROM Loader. The default values of the Asymmetric Pause and Symmetric Pause
bits are determined by the Manual Flow Control Enable Strap (manual_FC_strap_1 for Port
1 PHY, manual_FC_strap_2 for Port 2 PHY). When the Manual Flow Control Enable Strap
is 0, the Symmetric Pause bit defaults to 1 and the Asymmetric Pause bit defaults to the
setting of the Full Duplex Flow Control Enable Strap (FD_FC_strap_1 for Port 1 PHY,
FD_FC_strap_2 for Port 2 PHY). When the Manual Flow Control Enable Strap is 1, both
bits default to 0. Configuration strap values are latched upon the de-assertion of a chip-
level reset as described in Section 4.2.4, "Configuration Straps," on page 45. Refer to
Section 4.2.4, "Configuration Straps," on page 45 for configuration strap definitions.
Note 13.60 The default value of this bit is determined by the logical OR of the Auto-Negotiation Enable
strap (autoneg_strap_1 for Port 1 PHY, autoneg_strap_2 for Port 2 PHY) with the logical
AND of the negated Speed Select strap (speed_strap_1 for Port 1 PHY, speed_strap_2 for
Port 2 PHY) and the Duplex Select Strap (duplex_strap_1 for Port 1 PHY, duplex_strap_2
for Port 2 PHY). Table 13.9 defines the default behavior of this bit. Configuration strap
values are latched upon the de-assertion of a chip-level reset as described in Section
4.2.4, "Configuration Straps," on page 45. Refer to Section 4.2.4, "Configuration Straps,"
on page 45 for configuration strap definitions.
Table 13.9 10BASE-T Full Duplex Advertisement Default Value
autoneg_strap_x
0
0
0
0
1
1
1
1
speed_strap_x
0
0
1
1
0
0
1
1
duplex_strap_x
0
1
0
1
0
1
0
1
Default 10BASE-T Full Duplex Value
0
1
0
0
1
1
1
1
Note 13.61 The default value of this bit is determined by the logical OR of the Auto-Negotiation Enable
strap (autoneg_strap_1 for Port 1 PHY, autoneg_strap_2 for Port 2 PHY) and the negated
Speed Select strap (speed_strap_1 for Port 1 PHY, speed_strap_2 for Port 2 PHY).
Table 13.10 defines the default behavior of this bit. Configuration strap values are latched
upon the de-assertion of a chip-level reset as described in Section 4.2.4, "Configuration
Straps," on page 45. Refer to Section 4.2.4, "Configuration Straps," on page 45 for
configuration strap definitions.
Revision 1.3 (08-27-09)
200
DATASHEET
SMSC LAN9303/LAN9303i